XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 52

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000 Series Field Programmable Gate Arrays
mode runs at eight times the data rate of the other six
modes. A length count is not used in Express mode.
Express mode must be specified as an option to the Make-
Bits program, which generates the bitstream. The Express
mode bitstream is not compatible with the other six config-
uration modes.
Multiple slave devices with identical configurations can be
wired with parallel D0-D7 inputs.
devices can be configured simultaneously.
Pseudo Daisy Chain
Multiple devices with different configurations can be con-
nected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bit-
stream is used to configure the chain of Express mode
devices, but the input data bus must drive D0-D7 of each
device. Tie High the CS1 pin of the first device to be con-
figured. Connect the DOUT pin of each FPGA to the CS1
pin of the next device in the chain. The D0-D7 inputs are
wired to each device in parallel. The DONE pins are wired
together, with one or more internal DONE pull-ups acti-
vated. Alternatively, a 4.7 k external resistor can be used,
if desired. (See
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All XC4000EX devices in Express mode are synchronized
to the DONE pin. User I/O for each device become active
after the DONE pin for that device goes High. (The exact
timing is determined by MakeBits options.)
DONE pin is open-drain and does not drive a High value,
tying the DONE pins of all devices together prevents all
devices in the chain from going High until the last device in
the chain has completed its configuration cycle.
Because only XC4000EX and XC5200 devices support
Express mode, only these devices can be used to form an
Express mode daisy chain. XC5200 devices used in a
combined daisy chain with XC4000EX devices should be
configured as synchronized to DONE (MakeBits option
CCLK_SYNC or UCLK_SYNC), and their DONE pins wired
together with those of the XC4000EX devices.
Setting CCLK Frequency
For Master modes, CCLK can be generated in either of two
frequencies.
ranges from 0.5 MHz to 1.25 MHz (up to 10% lower for low-
voltage devices). In fast CCLK mode, the frequency ranges
from 4 MHz to 10 MHz (up to 10% lower for low-voltage
devices). The frequency is selected by an option when run-
ning MakeBits, the bitstream generation software tool. If an
XC4000-Series Master is driving an XC3000- or XC2000-
family slave, slow CCLK mode must be used. Slow mode is
the default.
4-56
In the default slow mode, the frequency
Figure 63 on page
76.)
In this way, multiple
Since the
Data Stream Format
The data stream (“bitstream”) format is identical for all con-
figuration modes, with the exception of Express mode. In
Express mode, the device becomes active when DONE
goes High, therefore no length count is required. Addition-
ally, CRC error checking is not supported in Express mode.
The data stream formats are shown in
mode data is shown with D0 at the left and D7 at the right.
For all other modes, bit-serial data is read from left to right,
and byte-parallel data is effectively assembled from this
serial bitstream, with the first bit in each byte assigned to
D0.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Express
mode). This header is followed by the actual configuration
data in frames. The length and number of frames depends
on the device type (see
frame begins with a start field and ends with an error check.
In all modes except Express mode, a postamble code is
required to signal the end of data for a single device. In all
cases, additional start-up bytes of data are required to pro-
vide four clocks for the startup sequence at the end of con-
figuration. Long daisy chains require additional startup
bytes to shift the last data through the chain. All startup
bytes are don’t-cares; these bytes are not included in bit-
streams created by the Xilinx software.
Table 21: XC4000-Series Data Stream Formats
LEGEND:
Fill Byte
Preamble Code
Length Count
Fill Bits
Start Field
Data Frame
CRC or Constant
Field Check
Extend Write Cycle
Postamble
Start-Up Bytes
Unshaded
Light
Dark
Data Type
11111111b
11110010b
FFFFFFh
—
11010010b
DATA(n-1:0)
11010010b
FFFFFFFFFFh
—
xxxxxxxxh
Once per bitstream
Once per data frame
Once per device
September 18, 1996 (Version 1.04)
Express Mode
Table 22
(D0-D7)
and
Table
Table
11111111b
0010b
COUNT(23:0)
1111b
0b
DATA(n-1:0)
xxxx (CRC)
or 0110b
—
01111111b
xxh
Modes (D0...)
All Other
21. Express
23).
Each