CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 16

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

Document #: 38-08027 Rev. *B
The Bus Activity bit is a “sticky” bit that indicates if any non-idle
USB event has occurred on the USB bus. The user firmware
should check and clear this bit periodically to detect any loss
of bus activity. Writing a “0” to the Bus Activity bit clears it while
writing a “1” preserves the current value. In other words, the
firmware can clear the Bus Activity bit, but only the SIE can set
it. The 1.024-ms timer interrupt service routine is normally
used to check and clear the Bus Activity bit. The following table
shows how the control bits are encoded for this register.
USB Device
USB Device Address A includes three endpoints: EPA0, EPA1,
and EPA2. End Point 0 (EPA0) allows the USB host to
recognize, set up, and control the device. In particular, EPA0
is used to receive and transmit control (including set-up)
packets.
USB Ports
The USB Controller provides one USB device address with
three endpoints. The USB Device Address Register contents
Table 18.USB Device Address Register
Table 19.USB Device EPA0, Mode Register
Table 20.USB Device Endpoint Mode Register
Control
Endpoint 0
Reserved
Received
Bits
Address
000
001
010
100
101
011
110
111
Device
Enable
Set-up
R/W
R/W
R/W
Addr: 0x14, 0x16
Addr:0x10
Addr:0x12
Endpoint 0
Received
Reserved
Address
Device
Not forcing (SIE controls driver)
Force SE0 (D+ LOW, D– LOW)
Force SE0 (D− LOW, D+ LOW)
Bit 6
R/W
R/W
R/W
Force K (D+ HIGH, D– LOW)
Force J (D+ LOW, D– HIGH)
In
Force D− LOW, D+ HiZ
Force D− HiZ, D+ LOW
Force D− HiZ, D+ HiZ
Control Action
Endpoint 0
Reserved
Received
Address
Device
Bit 5
R/W
R/W
R/W
Out
USB Device Endpoint Mode Register
USB Device EPA0, Mode Register
USB Device Address Register
Acknowledge
Acknowledge
Address
Device
Bit 4
R/W
R/W
R/W
are cleared during a reset, setting the USB device address to
zero and marking this address as disabled. Figure 18 shows
the format of the USB Address Register.
Bit 7 (Device Address Enable) in the USB Device Address
Register must be set by firmware before the serial interface
engine (SIE) will respond to USB traffic to this address. The
Device Address in bits [6:0] must be set by firmware during the
USB enumeration process to an address assigned by the USB
host that does not equal zero. This register is cleared by a
hardware reset or the USB bus reset.
Device Endpoints (3)
The USB controller communicates with the host using
dedicated FIFOs, one per endpoint. Each endpoint FIFO is
implemented as 8 bytes of dedicated SRAM. There are three
endpoints defined for Device “A” that are labeled “EPA0,”
“EPA1,” and EPA2.”
All USB devices are required to have an endpoint number 0
(EPA0) that is used to initialize and control the USB device.
End Point 0 provides access to the device configuration infor-
mation and allows generic USB status and control accesses.
End Point 0 is bidirectional as the USB controller can both
receive and transmit data.
The endpoint mode registers are cleared during reset. The
EPA0 endpoint mode register uses the format shown in Table
19.
Bits[7:5] in the endpoint 0 mode registers (EPA0) are “sticky”
status bits that are set by the SIE to report the type of token
that was most recently received. The sticky bits must be
cleared by firmware as part of the USB processing.
The endpoint mode registers for EPA1 and EPA2 do not use
bits [7:5] as shown in Table 20.
Address
Device
Mode
Mode
Bit 3
R/W
Bit 3
R/W
Bit 3
R/W
Address
Device
Mode
Mode
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
Address
Device
Mode
Mode
Bit 1
R/W
Bit 1
Bit 1
R/W
R/W
CY7C63413C
CY7C63513C
CY7C63613C
Page 16 of 32
Address
Device
Mode
Mode
Bit 0
R/W
Bit 0
Bit 0
R/W
R/W
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