CY7C63413-PVXC Cypress Semiconductor Corp, CY7C63413-PVXC Datasheet
CY7C63413-PVXC
Specifications of CY7C63413-PVXC
Related parts for CY7C63413-PVXC
CY7C63413-PVXC Summary of contents
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... CMOS outputs. The CY7C63413C/513C have 24 GPIO pins (Ports that are rated typical sink current. The CY7C63413C/513C has 8 GPIO pins (Port 3) that are rated typical sink current, which allows these pins to drive LEDs. ...
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... The Cypress microcontrollers use an external 6-MHz ceramic resonator to provide a reference to an internal clock generator. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6 and 12- MHz clocks that remain internal to the microcontroller. The CY7C63413C/513C/613C are offered with single EPROM options. The CY7C63413C, CY7C63513C CY7C63613C have 8 Kbytes of EPROM ...
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... P1[0] P0[ P0[6] P0[ P0[4] P0[ P0[2] P0[ P0[ XTAL PP OUT Vss 12 13 XTAL IN CY7C63413C 48-Pad Die OUT IN P3[3] P3[1] P2[7] P3[2] P3[0] P2[5] P2[6] P2[3] P2[4] P2[1] P2[2] P2[0] P1[7] P1[5] P1[6] P1[3] P1[4] P1[1] P1[2] DAC[7] P1[0] DAC[6] DAC[5] DAC[4] P0[7] P0[6] ...
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... Programming Model 14-bit Program Counter (PC) The 14-bit Program Counter (PC) allows access for kilobytes of EPROM using the CY7C63413C/513C/613C architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This is typically a jump instruction to a reset handler that initializes the application ...
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... For USB applications strongly recommended that the DSP is loaded after reset just below the USB DMA buffers. Address Modes The CY7C63413C/513C/613C microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. Document #: 38-08027 Rev. *B ...
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... AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 5 JACC 5 INDEX CY7C63413C CY7C63513C CY7C63613C operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 ...
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... USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here ( bytes) 0x1FDF 8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C) CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Data Memory Organization The CY7C63413C/513C/613C microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned after reset Address 8-bit PSP 0x00 8-bit DSP user 0xE8 0xF0 0xF8 Top of RAM Memory 0xFF Document #: 38-08027 Rev. *B into four areas: program stack, data stack, user variables and ...
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... W Watch Dog Reset clear [2] R/W DAC I/O W Interrupt enable for each DAC pin W Interrupt polarity for each DAC pin W One four bit sink current register for each DAC pin R/W Microprocessor status and control CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Significant Bit (MSB) of the 2-bit Watch Dog Timer Register transitions from LOW to HIGH. In addition to the normal reset 2.048 ms WDR goes high Execution begins at for 2.048 ms Reset Vector 0X00 Figure 3. Watch Dog Reset (WDR) CY7C63413C CY7C63513C CY7C63613C XTALOUT XTALIN voltage and the USB IO are at ...
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... Figure 4. Block Diagram of a GPIO Line Port 0 Data P0[4] P0[3] R/W R/W Port 1 Data P1[4] P1[3] R/W R/W Port 2 Data P2[4] P2[3] R/W R/W CY7C63413C CY7C63513C CY7C63613C GPIO Pin ESD P0[2] P0[1] P0[0] R/W R/W R/W P1[2] P1[1] P1[0] R/W R/W ...
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... Table 11. Port 0 Interrupt Enable P0[4] P0[3] P0[ Port 1 Interrupt Enable P1[4] P1[3] P1[ Port 2 Interrupt Enable P2[4] P2[3] P2[ Port 3 Interrupt Enable P3[4] P3[3] P3[ CY7C63413C CY7C63513C CY7C63613C P3[1] P3[0] R/W R/W High current outputs 3 typical DAC[1] DAC[0] R/W R/W P0[1] P0[ P1[1] P1[ P2[1] P2[ P3[1] P3[ ...
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... Port 2 Port 1 Config Bit 0 Config Bit 1 Config Bit Table 12.GPIO Configuration Register KΩ 4 bits Isink Isink DAC Register to Interrupt Controller Figure 5. Block Diagram of DAC Port CY7C63413C CY7C63513C CY7C63613C Interrupt Polarity - disabled disabled - + (default Port 1 Port 0 Port 0 Config Bit 1 Config Bit DAC ...
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... DAC[7]. DAC Port Interrupt Enable DAC[4] DAC[3] DAC[ DAC Port Interrupt Polarity DAC[4] DAC[3] DAC[ DAC Port Interrupt Polarity Isink[3] Isink[ CY7C63413C CY7C63513C CY7C63613C High current outputs 3 typical DAC[1] DAC[0] R/W R/W DAC[1] DAC[ DAC[1] DAC[ Isink Value Isink[1] Isink[0] ...
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... USB. PS/2 Operation PS/2 operation is possible with the CY7C63413C/513C/613C series through the use of firmware and several operating modes. The first enabling feature: 1. USB Bus reset on D+ and D− interrupt that can be disabled ...
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... Bit 4 Bit 3 R/W R/W USB Device EPA0, Mode Register Acknowledge Mode Bit 3 R/W R/W USB Device Endpoint Mode Register Acknowledge Mode Bit 3 R/W R/W CY7C63413C CY7C63513C CY7C63613C Device Device Address Address Bit 2 Bit 1 Bit 0 R/W R/W R/W Mode Mode Mode Bit 2 ...
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... Valid bit 6 is used for OUT and set-up tokens only. Data 0/1 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. USB Device Counter Registers Reserved Byte count Byte count Bit 3 Bit 2 R/W R/W R/W CY7C63413C CY7C63513C CY7C63613C Byte count Byte count Bit 1 Bit 0 R/W R/W Page [+] Feedback ...
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... Suspend, Wait Reset for Interrupt R/W R/W halted until a reset (Power On or Watch Dog). Notice, when writing to the processor status and control register, the run bit should always be written as a “1.” CY7C63413C CY7C63513C CY7C63613C Timer Timer Timer Bit 2 Bit 1 Bit 0 ...
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... ZF are restored and interrupts are enabled when the RETI instruction is executed. Global Interrupt Enable Register 4 3 DAC Reserved Interrupt Enable R/W USB End Point Interrupt Enable Register 4 3 Reserved Reserved CY7C63413C CY7C63513C CY7C63613C 1.024-ms 128-µsec USB Bus RST Interrupt Interrupt Interrupt Enable Enable Enable ...
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... The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. CY7C63413C CY7C63513C CY7C63613C Function Page ...
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... In and Out), but must be placed in the correct mode to function as such. Also a non-Control endpoint can be made to act as a Control endpoint placed in a non appropriate mode. A ‘check’ Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... ISR to unlock and get the mode register infor- mation. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. CY7C63413C CY7C63513C CY7C63613C What the SIE does to Mode bits ...
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... updates updates 1 updates updates updates CY7C63413C CY7C63513C CY7C63613C Set End Point Mode ACK response int ACK yes UC NoChange ignore yes UC NoChange ignore yes UC NoChange ignore no UC NoChange NAK yes UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no UC NoChange ...
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... updates updates updates CY7C63413C CY7C63513C CY7C63613C Set End Point Mode ACK response int Stall yes ignore ignore Stall yes ACK yes UC NoChange ignore yes UC NoChange ignore yes UC NoChange ignore no UC NoChange NAK yes UC NoChange ignore no UC NoChange ignore no UC NoChange ignore ...
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... Ohms 45% 65 range, as well as DAC outputs. CC (2) is limited to minimize Ground-Drop noise effects. SS CY7C63413C CY7C63513C CY7C63613C +0.5V CC +0.5V CC [3] Conditions Non USB activity (note 4) USB activity (note 5.5V CC Oscillator off, D– > Voh min V = 5.0V, ceramic resonator ...
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... To next transition, Figure 12 –150 150 ns To paired transition, Figure 12 of 50–600 pF. LOAD CY7C63413C CY7C63513C CY7C63613C Conditions All ports, HIGH to LOW edge Port 3, Vout = 1.0V (note 4) Port 0,1,2, Vout = 2.0V (note 4) Voh = 2.4V (all ports 0,1,2,3) (note 4) (note 14) Vout = 2.0 VDC (note 5) Vout = 2 ...
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... V crs V ol D− T PERIOD Differential Data Lines Document #: 38-08027 Rev CYC Figure 8. Clock Timing 90% 90% 10% 10% Figure 9. USB Data Signal Timing JR1 Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 10. Receiver Jitter Tolerance CY7C63413C CY7C63513C CY7C63613C T JR2 Page [+] Feedback ...
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... Shrunk Small Outline Package SP48 48-Lead SSOP Lead-Free Tape-reel P2 40-pin (600 mil) PDIP Lead-Free SP48 48-Lead SSOP Lead-Free SZ24.3 24-lead (300 mil) SOIC Lead-Free - Die Lead-Free CY7C63413C CY7C63513C CY7C63613C Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Operating Range ...
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... DAC4 516.25 32 Port0[6] 413.25 31 Port0[4] 98.00 30 Port0[2] 98.00 29 Port0[0] 98.00 28 DAC2 98.00 27 DAC0 98.00 26 XtalOut 98.00 25 XtalIn CY7C63413C CY7C63513C CY7C63613C X Y 1619.65 3023.60 1719.65 3023.60 1823.10 3023.60 1926.10 3023.60 2066.30 2657.35 2066.30 2554.35 2066.30 2451.35 2066.30 2348.35 2066.30 2245.35 2066.30 2142.35 2066 ...
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... Package Diagrams 48-Lead Shrunk Small Outline Package SP48 Document #: 38-08027 Rev. *B 40-Lead (600-Mil) Molded DIP P2 CY7C63413C CY7C63513C CY7C63613C 51-85061-*C 51-85019-*A Page [+] Feedback ...
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... MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE MIN. 3. DIMENSIONS IN INCHES MAX. 4. PACKAGE WEIGHT 0.65gms * 0.394[10.007] 0.419[10.642] SEATING PLANE 0.092[2.336] 0.105[2.667] 0.004[0.101] * CY7C63413C CY7C63513C CY7C63613C PART # S24.3 STANDARD PKG. SZ24.3 LEAD FREE PKG. * 0.0091[0.231] 0.015[0.381] 0.0125[0.317] 0.050[1.270] 51-85025-*C Page ...
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... Document History Page Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-speed High I/O, 1.5 -Mbps USB Controller Document Number: 38-08027 Issue REV. ECN NO. Date ** 116224 06/12/02 *A 237148 SEE ECN *B 418699 See ECN Document #: 38-08027 Rev. *B Orig. of Change Description of Change DSG Change from Spec number: 38-00754 to 38-08027 ...