CY7C63413-PVC Cypress Semiconductor Corp, CY7C63413-PVC Datasheet - Page 25

• Manufacturer Part Number: CY7C63413-PVC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PVC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1319

The ‘In’ column represents the SIE’s response to the token type.
A disabled endpoint will remain such until firmware changes it, and all endpoints reset to disabled.
Any Setup packet to an enabled and accepting endpoint will be changed by the SIE to 0001 (NAKing).Any mode which indicates
the acceptance of a Setup will acknowledge it.
Most modes that control transactions involving an ending ACK will be changed by the SIE to a corresponding mode which NAKs
follow on packets.
A Control endpoint has three extra status bits for PID (Setup, In and Out), but must be placed in the correct mode to function as
such. Also a non-Control endpoint can be made to act as a Control endpoint if it is placed in a non appropriate mode!
A ‘check’ on an Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG)
of 1.
Table 16-2. Decode table for Table 16-3 : “Details of Modes for Differing Traffic Conditions”
The response of the SIE can be summarized as follows:
(1) the SIE will only respond to valid transactions, and will ignore non-valid ones;
(2) the SIE will generate IRQ when a valid transaction is completed or when the DMA buffer is corrupted
(3) an incoming Data packet is valid if the count is <= 10 (CRC inclusive) and passes all error checking;
(4) a Setup will be ignored by all non Control endpoints (in appropriate modes);
(5) an In will be ignored by an Out configured endpoint and visa versa.
The In and Out PID status is updated at the end of a transaction.
The Setup PID status is updated at the beginning of the Data packet phase.
The entire EndPoint 0 mode and the Count register are locked to CPU writes at the end of any transaction in which an ACK is
transferred. These registers are only unlocked upon a CPU read of these registers, and only if that read happens after the
transaction completes. This represents about a 1 s window to which to the CPU is locked from register writes to these USB
registers. Normally the firmware does a register read at the beginning of the ISR to unlock and get the mode register informati on.
The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made
during the previous transaction!
Encoding
End Point Mode
3
Legend:
2
1
0
Token
Setup
In
Out
Properties of incoming packet
count
The number of received bytes
UC: unchanged
x: don’t care
available for Control endpoint only
buffer
The quality status of the DMA buffer
dval
The validity of the received data
DTOG
TX: transmit
RX: receive
Status bits
DVAL
25
COUNT
Setup
TX0: transmit 0-length packet
PID Status bits
In
Out
What the SIE does to Mode bits
ACK
Acknowledge phase completed
CY7C63411/12/13
CY7C63511/12/13
End Point
Mode
3
2 1 0
Interrupt?
Response
Int