MPC8541EVTAPF Freescale Semiconductor, MPC8541EVTAPF Datasheet - Page 34

• Manufacturer Part Number: MPC8541EVTAPF
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8541EVTAPF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 833MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 1.14V To 1.26V
• Rohs Compliant: Yes
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Local Bus
Table 31
bypassed.
34
Local bus cycle time
Internal launch/capture clock to LCLK delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to output high impedance for
LAD/LDP
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
6. The value of t
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
8. Guaranteed by characterization.
9. Guaranteed by design.
(reference)(state)
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
high (H), in this case for clock one(1). Also, t
high (H), with respect to the output (O) going invalid (X) or output hold time.
question for 3.3-V signaling levels.
through the component pin is less than or equal to the leakage current specification.
local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
complementary signals at OV
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
describes the general timing parameters of the local bus interface of the MPC8541E with the DLL
Parameter
LBOTOT
Parameter
for inputs and t
Table 30. Local Bus General Timing Parameters—DLL Enabled (continued)
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of
Table 31. Local Bus General Timing Parameters—DLL Bypassed
(First two letters of functional block)(reference)(state)(signal)(state)
DD
/2.
DD
/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LWE[0:1] = 11 (default)
LBKHOX
Configuration
Configuration
LWE[0:1] = 00
LWE[0:1] = 00
LWE[0:1] = 00
symbolizes local bus timing (LB) for the t
—
—
—
—
—
—
—
—
7
7
Symbol
Symbol
t
t
t
t
LBKHOZ2
LBKSKEW
t
t
t
t
t
t
LBKLOV1
LBKLOV2
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBKHKT
LBOTOT
(First two letters of functional block)(signal)(state)
t
LBK
1
1
Min
for outputs. For example, t
–1.3
–0.8
Min
6.0
1.8
5.2
5.1
1.5
—
—
—
—
LBK
LBK
Max
Max
150
2.8
4.2
3.4
0.5
2.0
0.7
2.2
—
—
—
—
—
—
clock reference (K) to go
clock reference (K) goes
Freescale Semiconductor
DD
of the signal in
Unit
Unit
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
LBIXKH1
Notes
Notes
5, 9
7, 9
3, 4
3, 4
3, 4
3, 4
2
8
6
3
3