GCIXP1200GC Intel, GCIXP1200GC Datasheet - Page 19

• Manufacturer Part Number: GCIXP1200GC
• Description: IC MPU NETWORK 232MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GC

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 232MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839429

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Specification Update
Non-aligned PCI DMA Transfers
If using non-longword aligned PCI or SDRAM addresses (address bit 1 or 0 =1) during DMA
Inbound or DMA Outbound transfers, either DMA channel 1 or DMA channel 2 may experience
unpredictable behavior.
Incorrect DMA operation may cause unpredictable results, including data errors.
Do not use non-longword aligned addresses for DMA transfers.
Fixed
SDRAM Memory Configuration.
A-stepping parts cannot correctly address 128 Mbytes of SDRAM. When SDRAM_MEMCTL0 is
set for an SDRAM configuration with a Row Address Width (RAS) of 12 bits and a Column
Address Width (CAS) of 10 bits (bits [7:0] = 0xCA), the MADR[13] pin, which is the high order
bank select, is never asserted.
When the IXP1200 is configured for 128 Mbytes of SDRAM, accesses to the upper 64 Mbytes of
SDRAM result in the lower 64 Mbytes of SDRAM being accessed.
Do not use the 128 Mbyte SDRAM configuration with A-stepping parts.
Fixed
IX Bus Contention in Shared IX Bus Mode
In shared IX Bus mode, using the TK_IN pin to configure the initial IX Bus Owner and Ready Bus
Master Mode could result in improper initialization. As a result, more than one IXP1200 may be
the initial IX Bus Owner and Ready Bus Master.
This erratum causes contention on the IX Bus and the Ready Bus. It is also possible that the devices
could initialize to the opposite state (not initial IX Bus Owner, Ready Bus Slave), in which case no
device controls the Ready Bus as master.
Use software to configure the initial IX Bus Owner and Ready Bus Master Mode instead of using
the TK_IN strapping option. Pulldown the TK_IN inputs to all IXP1200s on a Shared IX Bus to
inhibit initial IX Bus Owner and Ready Bus Master Mode. This ensures that no IXP1200 will be
the initial IX Bus Owner and that all IXP1200s will be Ready Bus slaves. Boot software can then
initialize one IXP1200 to initial IX Bus Owner and Ready Bus Master Mode by writing
RDYBUS_TEMPLATE_CTL[8]=1. It is recommended to perform this operation as quickly as
possible after reset to minimize the length of time the IX Bus and Ready Bus float.
NoFix
Intel
®
IXP1200 Network Processor
Errata
19