GCIXP1200GC Intel, GCIXP1200GC Datasheet
GCIXP1200GC
Specifications of GCIXP1200GC
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GCIXP1200GC Summary of contents
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... Dual DMA channels Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Datasheet Industry Standard 64-bit SDRAM Interface — ...
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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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... Serial Port (UART) Pins .........................................................................36 6.3.7 PCI Interface Pins ..................................................................................37 6.3.8 Power Supply Pins .................................................................................40 6.3.9 IEEE 1149.1 Interface Pins ....................................................................41 6.3.10 Miscellaneous Test Pins.........................................................................41 6.3.11 Pin Usage Summary ..............................................................................42 6.4 Pin/Signal List......................................................................................................43 6.5 Signals Listed in Alphabetical Order ...................................................................47 Datasheet ® Intel IXP1200 Network Processor iii ...
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... Intel IXP1200 Network Processor 6.6 IX Bus Pins Function Listed by Operating Mode................................................. 52 6.7 IX Bus Decode Table Listed by Operating Mode Type ....................................... 62 6.8 Pin State During Reset........................................................................................ 64 6.9 Pullup/Pulldown and Unused Pin Guidelines ...................................................... 66 7.0 Electrical Specifications ................................................................................................... 67 7.1 Absolute Maximum Ratings ................................................................................ 67 7.2 DC Specifications................................................................................................ 70 7.2.1 Type 1 Driver DC Specifications ...
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... Bidirectional IX Bus Timing - Consecutive Transmits with Prepend, EOP 99 38 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, No EOP.............100 39 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 16th Data Return with Status ....................................................................................101 40 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 15th Data Return with Status ............................................................................102 Datasheet ® Intel IXP1200 Network Processor v ...
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... Intel IXP1200 Network Processor 41 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 14th Data Return with Status .................................................................................... 103 42 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 1st Through 13th Data Return with Status (13th Data Return Shown) ................... 104 43 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP, 64-Bit Status ...
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... IX Bus Decode Table Listed by Operating Mode Type .......................................62 29 Pin State During Reset........................................................................................64 30 Absolute Maximum Ratings.................................................................................67 31 Functional Operating Range ...............................................................................68 32 Typical and Maximum Power ..............................................................................68 33 Maximum and Typical Bus Loading Used for the Power Calculations ................68 Datasheet ® Intel IXP1200 Network Processor vii ...
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... Intel IXP1200 Network Processor 34 I1, I3, O1, O3, O4, and O5 Pin Types ................................................................. and O2 Pin Types ........................................................................................... 71 36 Overshoot/Undershoot Specifications................................................................. 71 37 PXTAL Clock Inputs ............................................................................................ MHz PCI Clock Signal AC Parameters .......................................................... MHz PCI Clock Signal AC Parameters .......................................................... MHz PCI Signal Timing .................................................................................. MHz PCI Signal Timing .................................................................................. 75 42 Reset Timings Specification................................................................................ 76 43 IEEE 1149 ...
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... GPIO RTC SRAM Unit Micro- engine 1 FBI Unit Scratchpad Memory (4 Kbyte) Hash Unit IX Bus Interface Micro- engine 4 Intel IXP1200 Network Processor ® Intel IXP1200 Network Processor PCI Unit 32-bit bus 64-bit bus SDRAM Unit Micro- Micro- engine engine 2 3 Micro- Micro- ...
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... Figure 2. IXP1200 System Block Diagram SSRAM (8 Mbytes Max) Buffer BootROM (8 Mbytes Max) SlowPort Devices (2 Mbytes Max PCI Bus (33-66Mhz) 32 Control ® Intel Data 32 IXP1200 r Processo 64 IX Bus Data Control and Status Network Interface Devices Network Command SDRAM (256 Mbytes Data 64 Max) ...
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... Support chips from Intel can assist the system designer in using the IXP1200 in these multiprocessor designs. A full suite of software tools is available from Intel for Microengine code development, simulation, and target hardware debugging. These tools can be used in conjunction with third-party StrongARM* software tools and Realtime Operating Systems to build a complete embedded solution ...
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... IXP1200 Network Processor 5.0 Functional Units 5.1 StrongARM* Core The StrongARM* core is the same industry standard 32-bit RISC processor as used in the Intel * StrongARM SA-1100 compatible with the StrongARM* processor family currently used in applications such as network computers, PDAs, palmtop computers and portable telephones. The differentiating feature of the StrongARM* processor is that it provides very high performance in a low-power, compact design ...
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... Table 25 tri-state. The IX Bus and Intel devices using the IX Bus, such as the 21440 and IXF1002, observe a pipelined bus protocol. When receive transfers are terminated early, the pipeline continues to cause several extra bus cycles depending on when the EOP/EOP_RX signal was asserted. Data is a “don't ...
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... Intel IXP1200 Network Processor care” for these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a possible status transfer if the device were programmed to support it. Slave devices must drive valid logic levels on the FDAT data pins during these cycles. ...
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... The IXP1200 supports two high performance memory units. The SRAM Unit provides fast memory that can be used to store look-up tables. The SDRAM Unit provides lower cost memory for forwarding information and transmit queues. Both units contain features that improve memory bandwidth utilization. Datasheet ® Intel IXP1200 Network Processor 15 ...
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... Intel IXP1200 Network Processor 5.4.1 SDRAM Unit The IXP1200 provides an SDRAM Unit to access low cost, high bandwidth memory for mass data storage. The StrongARM* core address space allows up to 256 Mbytes of SDRAM to be addressed. The SDRAM interface operates at half the core frequency (0.5*F bandwidth of 928 Mbytes per second at 232 MHz ...
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... Mbytes 8 32 Mbytes 4 64 Mbytes 8 32 Mbytes 4 64 Mbytes 8 64 Mbytes 4 128 Mbytes 8 128 Mbytes 4 256 Mbytes 8 Datasheet Intel Size Configuration Internal DRAM (per bank) Banks 16 Mbit 512 K x 16-bit 2 16 Mbit 8-bit 2 64 Mbit 16-bit 2 64 Mbit 8-bit 2 64 Mbit ...
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... Intel IXP1200 Network Processor 5.4.4 SRAM Unit The IXP1200 provides an SRAM Unit for very high bandwidth memory for storage of lookup tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM ( Mbytes), BootROM ( Mbytes) for booting, and 2 Mbytes of SlowPort address space for peripheral device access ...
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... SRAM Types Supported Pipeline Burst DCD (double cycle deselect) type: tKQmax=4.2 ns, 3.3 V. Flowthru type: tKQmax= 9 ns, 3.3 V. Note: Other SSRAM devices, including single cycle deselect, are not supported. Datasheet ® Intel IXP1200 Network Processor Figure 73 which illustrates this example. The 19 ...
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... Intel IXP1200 Network Processor 5.4.4.2 SRAM Configurations Table 6. SRAM Configurations Total Memory 1 Mbytes 2 Mbytes 2 Mbytes 4 Mbytes 4 Mbytes 8 Mbytes (maximum) 5.4.4.3 BootROM Configurations Table 7. BootROM x32 Sample Configurations Total Memory 512 Kbytes 2 Mbytes 4 Mbytes 6 Mbytes 8 Mbytes Table 8. BootROM x16 Sample Configurations ...
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... PCI devices are supported only, the IXP1200 and a second PCI device. To increase the number of PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI bridge device, such the Intel 21150, 21152, or 21153 is required. Both PCI Initiator and Target cycles are supported target device, the IXP1200 responds as a Medium Speed device asserting DEVSEL# two PCI_CLK cycles after FRAME# is asserted ...
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... Intel IXP1200 Network Processor 5.5.1 PCI Arbitration and Central Function Support The IXP1200 contains an optional arbiter to support up to three PCI Bus masters. This includes the IXP1200 plus two external PCI Bus master devices. The external masters are supported by two request signals, REQ#[1:0], and two grant signals GNT#[1:0]. ...
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Output Pin RESET_OUT# ext_rst Soft reset timer rst_in_sync start !zero 140 cycle counter Core clock [31] [30] [29] [28:19] [18] [17] cmd SA PCI sram sdram res arb Core reset reset reset reset reset reset Internal Reset Signals strongarm_rst pci_rst ...
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... Intel IXP1200 Network Processor 5.6.1 Hardware Initiated Reset The IXP1200 provides the RESET_IN# pin so that an external device can reset the IXP1200. Asserting this pin resets the internal functions and generates an external reset via the RESET_OUT# pin. Upon power-up, RESET_IN# must remain asserted for 150 ms after VDD and VDDX are stable to properly reset the IXP1200 and ensure that the PXTAL clock input and PLL Clock generator are stable ...
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... SLOW_RD# SP_CE# SLOW_EN# MADR[14:0] MDATA[63:0] RAS# CAS# WE# DQM SDCLK VDD VDDX VDDP1 VSS VSSP1 VDD_REF ® Intel IXP1200 Network Processor PORTCTL#[3:0] FPS[2:0] FCLK FDAT[63:0] FBE#[7:0] SOP/SOP_RX EOP/EOP_RX TXASIS/TXERR IX Bus RXFAIL Interface FAST_RX1 FAST_RX2 RDYCTL#[4]/FC_EN1#/RXPEN# RDYCTL#[3:0] RDYBUS[7:0] ...
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... Intel IXP1200 Network Processor 6.2 Pin Type Legend The IXP1200 signals are categorized into one of several groups: Processor Support, Miscellaneous/Test, IEEE 1149.1, SRAM Interface, SDRAM Interface, IX Bus Interface, General Purpose, Serial Port, and PCI Interface. Table 10 defines the signal type abbreviations used in the Pin Description section. ...
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... Processor Support Pins Table 11. Processor Support Pins Processor Support Signal Names PXTAL CINT# RESET_OUT# RESET_IN# Totals: Datasheet Intel Pin # Type Total Input connection for system oscillator. Typically 3.6864 MHz. Drives internal PLL clock generator. Level-sensitive interrupt input to the StrongARM* Y28 ...
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... Intel IXP1200 Network Processor 6.3.2 SRAM Interface Pins Table 12. SRAM Interface Pins SRAM Interface Signal Names A[18:0] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] DQ[31:0] [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] ...
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... Note that this pin is driven as an output until SRAM_CSR[19] is set. Slow device enable Slow device (BootROM or SlowPort), Y29 O4 1 1=SRAM. W29 O4 1 Slow asynchronous interface chip enable output. Y31 O4 1 Slow asynchronous interface read enable output. 65 ® Intel IXP1200 Network Processor Pin Descriptions ). core 29 ...
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... Intel IXP1200 Network Processor 6.3.3 SDRAM Interface Pins Table 13. SDRAM Interface Pins SDRAM Interface Pin # Signal Names MADR[14:0] [14] AK5 [13] AD1 [12] AC3 [11] AC2 [10] AC1 [9] AB3 [8] AA4 [7] AB2 [6] AB1 [5] AA3 [4] AA1 [3] Y3 [2] W4 [1] Y2 [0] Y1 MDATA[63:0] [63] AH6 [62] AJ5 [61] AL4 [60] AK4 [59] AH5 [58] ...
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... D1 [0] D2 RAS# W2 CAS# W3 WE# W1 DQM V3 SDCLK AD2 Totals: Datasheet Intel Type Total Row Address Select output Precharge cycle indicated if asserted with WE Column Address Select output Write Enable output. SDRAM data control output. SDRAMs use this signal to enable O4 1 their data buffers to drive MDATA[63:0] on reads, or enable the SDRAM to accept input data from MDATA[63:0] for writes ...
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... Intel IXP1200 Network Processor 6.3.4 IX Bus Interface Pins Table 14. IX Bus Interface Pins IX Bus Signal Pin # Names FCLK AB30 PORTCTL#[3:0] [3] AC30 [2] AC31 [1] AB29 [0] AA28 FPS[2:0] [2] AC29 [1] AD31 [0] AD30 FDAT[63:0] [63] AC28 [62] AD29 [61] AE31 [60] AE30 [59] AF31 [58] AF30 [57] AF29 [56] AG31 [55] AG30 [54] ...
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... AK11 TXASIS/TXERR AL10 RXFAIL AK10 FAST_RX1 AH11 Datasheet Intel Type Total Bidirectional Byte Enables. 64-bit bidirectional IX Bus mode. Bits [7:0] indicate transmit and receive valid bytes on FDAT[63:0]. 32-bit unidirectional IX Bus mode. Bits [7:4] are used to indicate I2/O5/ 8 valid transmit bytes on FDAT[63:32] and bits [3:0] are used to TS indicate valid receive bytes on FDAT[31:0] ...
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... Intel IXP1200 Network Processor Table 14. IX Bus Interface Pins (Continued) IX Bus Signal Pin # Names FAST_RX2 AJ10 RDYCTL#[4]/ FC_EN1#/ AK6 RXPEN# RDYCTL#[3:0] [3] AL6 [2] AJ7 [1] AH8 [0] AK7 RDYBUS[7:0] [7] AL9 [6] AK9 [5] AJ9 [4] AL8 [3] AK8 [2] AH9 [1] AJ8 [0] AL7 SOP/SOP_RX AH12 34 Type Total Ready Input from Fast Port 1 (i.e., Gigabit port). Pulldown through ...
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... AJ6 SOP_TX TK_REQ_IN/ AL5 EOP_TX TK_OUT AA29 TK_IN AB31 Totals: Datasheet Intel Type Total End of Packet Indication. • Receive End of Packet Input in 32-bit unidirectional IX Bus mode. • Input/Output in 64-bit bidirectional IX Bus mode. I1/O4/ 1 EOP/EOP_RX is Transmit End of Packet output according to TS values programmed in the TFIFO control field. Is Receive End of Packet input during receive cycles. • ...
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... Intel IXP1200 Network Processor 6.3.5 General Purpose I/Os Table 15. General Purpose I/Os General Purpose I/O Pin # Signal Names GPIO[3:1] [3] A25 [2] B25 [1] D24 GPIO[0]/ FC_EN0#/ C25 TXPEN Totals: 6.3.6 Serial Port (UART) Pins Table 16. Serial Port (UART) Pins Serial Port (UART) Signal ...
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... FRAME# C13 IRDY# A12 TRDY# B12 STOP# C12 Datasheet Intel Type Total Address/data. These signals are multiplexed address and data bus. The IXP1200 receives addresses as target and drives I2/O2/ 32 addresses as master. It receives write data and drives read data TS as target. It drives write data and receives read data as master. ...
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... Intel IXP1200 Network Processor Table 17. PCI Interface Pins (Continued) PCI Interface Pin # Signal Names DEVSEL# D13 IDSEL C16 PERR# A11 SERR# B11 PCI_IRQ# A22 PCI_RST# C21 PCI_CLK D20 A24 PCI_CFN[1:0] C23 38 Type Total Device Select. Indicates that the target has decoded its address ...
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... B21 REQ#[0] A21 GNT#[1] C20 REQ#[1] D19 Totals: Datasheet Intel Type Total PCI Bus Master Grant 1. Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an output to grant a PCI device 1 control of the PCI Bus. (The IXP1200 is PCI device 0 in this case) I2/O2 1 Internal PCI arbiter is disabled (PCI_CFN[1:0] = 00): Pin is an input that indicates that the IXP1200 can assert FRAME# and become the bus master ...
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... Intel IXP1200 Network Processor 6.3.8 Power Supply Pins Table 18. Power Supply Pins Supply Signal Pin # Names VDD A19, B19, B27, H31, J29, K2, L4, Y4, AA2, AA30, AA31, AC4, AD3, AD28, AE29, AG4, AG28 Total VDD pins VDDX A1, A31,B2, B30, C3, C29, D4, D7, D10, D14, D18, D22, D25, D28, G4, G28, K4, K28, P4, ...
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... Used for Intel test purposes only. When high, bypasses PLL for I1 1 Test/debug. Must be low for normal system operation. Used for Intel test purposes only. Used as clock input when bypassing the internal PLL clock generator. For Normal I1 1 operation, this pin should not be allowed to float. It should be pulled up or pulled down through the proper value resistor ...
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... Intel IXP1200 Network Processor 6.3.11 Pin Usage Summary Table 21. Pin Usage Summary Type Inputs Outputs Bidirectional Total Signal Power Overall Totals: 42 Quantity 21 68 235 324 108 432 Datasheet ...
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... A24 PCI_CFN[0] A25 GPIO[3] A26 CE#[3] A27 CE#[0] A28 A[18] A29 VSS A30 VSS A31 VDDX B1 VSS B2 VDDX B3 VSS Datasheet ® Intel IXP1200 Network Processor Pin Signal Name Number Number B4 PXTAL C7 B5 TSTCLK C8 B6 AD[ AD[4] C10 B8 CBE#[0] C11 B9 AD[10] C12 B10 ...
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... Intel IXP1200 Network Processor Table 22. Pin Table in Pin Order (Continued) Pin Signal Name Number D10 VDDX D11 AD[13] D12 PAR D13 DEVSEL# D14 VDDX D15 AD[18] D16 AD[23] D17 AD[26] D18 VDDX D19 REQ#[1] D20 PCI_CLK D21 TDO D22 VDDX ...
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... SP_CE# W30 SOE# W31 SCLK Y1 MADR[0] Y2 MADR[1] Y3 MADR[3] Y4 VDD Y28 CINT# Y29 SLOW_EN# Y30 SWE# Datasheet ® Intel IXP1200 Network Processor Pin Signal Name Number Number Y31 SLOW_RD# AE28 AA1 MADR[4] AE29 AA2 VDD AE30 AA3 MADR[5] AE31 AA4 MADR[8] AF1 ...
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... Intel IXP1200 Network Processor Table 22. Pin Table in Pin Order (Continued) Pin Signal Name Number AH18 VDDX AH19 FDAT[20] AH20 FDAT[24] AH21 FDAT[28] AH22 VDDX AH23 FDAT[35] AH24 FDAT[39] AH25 VDDX AH26 FDAT[46] AH27 FDAT[50] AH28 VDDX AH29 VSS AH30 FDAT[51] ...
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... A[6] A[7] A[8] A[9] AD[0] AD[1] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[2] AD[20] AD[21] Datasheet Intel Pin Pin Signal Name Number Number J28 AD[22] A15 H29 AD[23] D16 E30 AD[24] A16 F28 AD[25] C17 E29 AD[26] ...
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... Intel IXP1200 Network Processor Table 23. Pin Table in Alphabetical Order (Continued) Signal Name FBE#[4] FBE#[5] FBE#[6] FBE#[7] FCLK FDAT[0] FDAT[1] FDAT[10] FDAT[11] FDAT[12] FDAT[13] FDAT[14] FDAT[15] FDAT[16] FDAT[17] FDAT[18] FDAT[19] FDAT[2] FDAT[20] FDAT[21] FDAT[22] FDAT[23] FDAT[24] FDAT[25] FDAT[26] FDAT[27] FDAT[28] FDAT[29] ...
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... MDATA[30] MDATA[31] MDATA[32] MDATA[33] MDATA[34] MDATA[35] MDATA[36] MDATA[37] MDATA[38] MDATA[39] MDATA[4] MDATA[40] MDATA[41] MDATA[42] MDATA[43] MDATA[44] MDATA[45] MDATA[46] MDATA[47] MDATA[48] MDATA[49] MDATA[5] Datasheet Intel Pin Pin Signal Name Number Number J2 MDATA[50] AF1 J1 MDATA[51] AF2 E3 MDATA[52] AF3 K3 MDATA[53] AG1 K1 MDATA[54] AG2 L3 MDATA[55] ...
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... Intel IXP1200 Network Processor Table 23. Pin Table in Alphabetical Order (Continued) Signal Name TRDY# TRST# TSTCLK TXASIS TXD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_REF VDDP1 VDDX VDDX VDDX VDDX ...
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... Table 23. Pin Table in Alphabetical Order (Continued) Signal Name VSS VSSP1 WE# Datasheet Intel Pin Pin Signal Name Number Number AL30 A4 W1 ® IXP1200 Network Processor Pin Signal Name Number 51 ...
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... IX Bus Pins Function Listed by Operating Mode Figure 7 through Figure 11 to one or more MAC devices and is accompanied by a pin description for the IX Bus in that mode. Figure 7. 64-Bit Bidirectional IX Bus, 1-2 MAC Mode ® Intel IXP1200 Processor GPIO[0]/FC_EN0#/TXPEN RDYCTL[4]/FC_EN1#/RXPEN# PORTCTL#[3:0] TK_REQ_OUT/SOP_TX ...
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... FPS[2:0] FDAT[63:0] FBE#[7:0] SOP/SOP_RX EOP/EOP_RX TxASIS/TxERR RxFAIL 3.3V not used ® Intel IXP1200 Network Processor Dual Fast Port Device CINT_L[1:0] ® (Intel IXF1002) [1:0] FLCT[1:0] FLCT_LAT [1:0] TxRDY[1:0] TxCTL_L RxRDY[1:0] RxCTL_L RxSEL_L TxSEL_L FPS FDAT[63:0] FBE_L[7:0] SOP EOP TxASIS/TxERR ...
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... Intel IXP1200 Network Processor Table 24. 64-Bit Bidirectional IX Bus, 1-2 MAC Mode Signal GPIO[3:1] GPIO[0]/FC_EN0#/ TXPEN RDYCTL#[3:0] RDYCTL#[4]/FC_EN1#/ RXPEN# RDYBUS[7:0] PORTCTL#[3:0] FPS[2:0] SOP/SOP_RX TK_REQ_OUT/ SOP_TX EOP/EOP_RX TK_REQ_IN/EOP_TX TK_IN TK_OUT RXFAIL TXASIS/TXERR FBE#[7:0] FDAT[63:0] FAST_RX1 FAST_RX2 54 Description Active High, input/output assigned to StrongARM* core not used for MAC interface ...
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... RDYBUS[7:0] [31:0] RDYCTL#[3:0] 5 > 32 FCLK [15:0] 4 > 16 PORTCTL#[3:0] FCLK FPS[2:0] FDAT[63:0] FBE#[7:0] SOP/SOP_RX EOP/EOP_RX TxASIS/TxERR RxFAIL not used 3.3V ® Intel IXP1200 Network Processor 3.3V MAC0 wireor CINT[7: FLCTL[7:0] [19] e FCLK RxRDY[7:0] TxRDY[7:0] [27] RxCTL# [23] TxCTL# [1] RxSEL# [0] ...
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... Intel IXP1200 Network Processor Table 25. 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) Signal GPIO[3:1] GPIO[0]/FC_EN0#/ TXPEN RDYCTL#[4:0] RDYBUS[7:0] PORTCTL#[3:0] FPS[2:0] SOP/SOP_RX TK_REQ_OUT/ SOP_TX EOP/EOP_RX TK_REQ_IN/EOP_TX TK_IN TK_OUT RXFAIL TXASIS/TXERR 56 Description Active High input/output assigned to StrongARM* core not used for MAC interface. ...
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... TXASIS/TXERR RXFAIL SOP/SOP_RX EOP/EOP_RX Datasheet Intel Description Active Low, byte enables for FDAT [64:0]. Tri-stated in shared IX Bus Mode when the IXP1200 does not own the IX Bus. Active High, read and write data. Tri-stated in shared IX Bus mode when the IXP1200 does not own the IX Bus. ...
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... Intel IXP1200 Network Processor Figure 10. 32-Bit Unidirectional IX Bus, 1-2 MAC Mode ® Intel IXP1200 Processor GPIO[0]/FC_EN0#/TXPEN RDYCTL[4]/FC_EN1#/RXPEN# Receive Transmit TK_REQ_OUT/SOP_TX TK_REQ_IN/EOP_TX 58 CINT# RDYBUS[7:0] [0] RDYCTL#[3:0] [1] [0] PORTCTL#[1:0] FDAT [31:0] FBE#[3:0] FPS[2:0] RxFAIL SOP/SOP_RX EOP/EOP_RX ...
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... RDYCTL#[3:0] RDYBUS[7:0] TK_IN TK_OUT FAST_RX1 FAST_RX2 Datasheet Intel Description Active high outputs, Transmit Port Select [2:0]. Active Low, output. Transmit Device Selects [1:0]. Active High, output, transmit Start of Packet. TK_REQ_OUT/SOP_TX is output during transmit according to value programmed in the TFIFO control field. ...
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... Intel IXP1200 Network Processor Figure 11. 32-bit Unidirectional IX Bus, 3+ MAC Mode (3-4 MACs Supported) ® Intel IXP1200 Processor Receive RDYCTL#[4]/FC_EN1#/RXPEN# Transmit GPIO[0]/FC_EN0#/TXPEN TK_REQ_OUT/SOP_TX TK_REQ_IN/EOP_TX 60 CINT#[0] [15:0] 4 > 16 RDYCTL#[3:0] decoder FCLK RDYBUS[7:0] 2 > 4 decoder [3:0] e [0] Q PORTCTL#[1:0] ...
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... RDYCTL#[3:0] RDYBUS[7:0] TK_IN TK_OUT FAST_RX1 FAST_RX2 Datasheet Intel Description Active high outputs, Transmit Port Selects [2:0]. Active Low, outputs. Used with GPIO[0]/FC_EN0#/TXPEN for transmit device select via external 2-to-4 decoder. Active High, output, transmit enable. Used with PORTCTL#[3:2] for transmit device select via external 2-to-4 decoder ...
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... Intel IXP1200 Network Processor 6.7 IX Bus Decode Table Listed by Operating Mode Type Table 28. IX Bus Decode Table Listed by Operating Mode Type PIN NAME Bidirectional 1-2 1110 MAC0 RxSEL 1101 MAC1 RxSEL PORTCTL#[3:0] 1011 MAC0 TxSEL 0111 MAC1 TxSEL 1111 No Select ...
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... MAC6 Rx 00111 MAC4 Tx 00110 MAC5 Tx 00101 MAC6 Tx 00011 MAC4 Flw Ctl enable 00010 MAC5 Flw Ctl enable 00001 MAC6 Flw Ctl enable ® Intel IXP1200 Network Processor 32-bit 32-bit Unidirectional 1-2 Unidirectional 3+ MAC mode MAC mode Tx EOP Tx EOP MAC1 Flw Ctl ...
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... Intel IXP1200 Network Processor 6.8 Pin State During Reset Table 29 summarizes IXP1200 pin states during reset. Table 29. Pin State During Reset Function SRAM SCLK SRAM A[17:0] SRAM DQ[31:0] SRAM CE#[3:0] SRAM SLOW_EN# SRAM SOE# SRAM SWE# SRAM HIGH_EN#/RDY# SRAM ...
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... TK_REQ_OUT/SOP_TX IX Bus RXFAIL IX Bus TK_IN IX Bus TK_OUT IX Bus GPIO[3] IX Bus GPIO[2] IX Bus GPIO[1] IX Bus GPIO[0]/FC_EN0#/TXPEN Datasheet Intel Pin Name Pin Reset State input Hi-Z PCI_CFN[1:0]=00, PCI_RST=Hi-Z PCI_CFN[1:0]=11, PCI_RST=output, low Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PCI_CFN[1:0]=00, GNT#[1:0]=Hi-Z PCI_CFN[1:0]=11, ...
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... Intel IXP1200 Network Processor Table 29. Pin State During Reset (Continued) Function Misc Test TCK_BYP Misc Test TSTCLK Misc Test SCAN_EN Processor PXTAL Support Processor CINT# Support Processor RESET_IN# Support Processor RESET_OUT# Support Serial RXD Serial TXD IEEE 1149.1 TCK IEEE 1149.1 TDI IEEE 1149 ...
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... V delta Datasheet Table 30 lists the absolute maximum ratings for the Parameter Minimum --- j 1.9 V 3.0 V -55°C 0.0 V ® Intel IXP1200 Network Processor ) of 232 MHz at a junction core (Table 30) is not ) must not be delta Maximum Comment 100°C 3 supply 3.6 V 3.3 V supply 125° ...
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... Intel IXP1200 Network Processor The power specifications listed below are based on the following assumption: • PCI Bus Frequency (PCI_CLK MHz. Table 31. Functional Operating Range Parameter Operating temperature range Supply voltage (core and PLL), VDD, VDDP1 Supply voltage (I/O), VDDX, VDDREF Table 32 ...
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... Note: Refer to the IXP1200 Network Processor Family Heatsinks: ja and Airflow - Application Note for additional information on heatsinks and thermal management. Datasheet 100 200 300 400 Airflow (LFM) Figure 12 was tested on an IXP1200 Network Processor ® Intel IXP1200 Network Processor Bare Package 0.5" Tall HS 0.745" Tall 1.10" Tall HS Fan HS 500 600 700 800 A8541-01 ...
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... Intel IXP1200 Network Processor 7.2 DC Specifications The IXP1200 supports two fundamental I/O buffer Types: Type 1 and Type 2. The Pin Description section defines which pins use which I/O buffer type. The driver characteristics are described in the following sections. Please note that IXP1200 input pins are not 5 V tolerant. Devices driving the IXP1200 must provide 3 ...
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... Undershoot Overshoot -0.75 V VDDX + 0.7 V -0.7 V VDDX + 0.65 V -0.7 V VDDX + 0.6 V -0.75 V VDDX + 1.0 V -0.7 V VDDX + 0.65 V ® Intel IXP1200 Network Processor Minimum Maximum 0.5 x VDDX VDD_REF + 0.5 V --- 0.3 x VDDX 0.9 x VDDX --- --- 0.1 x VDDX - ...
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... Intel IXP1200 Network Processor 7.3 AC Specifications 7.3.1 Clock Timing Specifications The ac specifications consist of input requirements and output responses. The input requirements consist of setup and hold times, pulse widths, and high and low times. Output responses are delays from clock to signal. The ac specifications are defined separately for each clock domain within the IXP1200 ...
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... Volts < 40%-60% T cyc T high low Parameter Minimum PCI_CLK cycle time 15 PCI_CLK high time 6 PCI_CLK low time PCI_CLK slew rate 1.5 F /PCI Clock Ratio 2:1 core ® Intel IXP1200 Network Processor A6992-01 Maximum Unit ns --- ns --- ns 4 V/ns 73 ...
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... Intel IXP1200 Network Processor Table 39. 33 MHz PCI Clock Signal AC Parameters Symbol T cyc T high T low 1. 0.2 VDDX to 0.6 VDDX. 2. Not tested. Guaranteed by design. Figure 15. PCI Bus Signals PCI_CLK Outputs Inputs Note 0.4 VDDX for 3.3 volt PCI signals test 74 Parameter ...
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... These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2. 2. Point-to-point signals are REQ#, GNT#. 3. Not tested. Guaranteed by design. 4. Bused signals are AD, CBE#, PAR, PERR#, SERR#, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#. Datasheet Intel Parameter Minimum 1.5 1.5 2 ...
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... Intel IXP1200 Network Processor 7.3.5 Reset 7.3.5.1 Reset Timings Specification Table 42 shows the reset timing specifications for RESET_IN# and RESET_OUT#. Table 42. Reset Timings Specification Symbol RESET_IN# asserted after power t RST stable. t GPIO[3] setup to reset sample edge. SG GPIO[3] hold from reset sample ...
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... Caution: A clock signal must be applied to the core of the IXP1200 when using IEEE 1149.1 functions. The PXTAL clock input should be active, or, if using bypass mode, (TCK_BYP = 1) TSTCLK should be active. Failure to observe this rule may cause device damage. Datasheet ® Intel IXP1200 Network Processor 77 ...
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... Intel IXP1200 Network Processor 7.3.6.1 IEEE 1149.1 Timing Specifications Figure 17. IEEE 1149.1/Boundary-Scan General Timing 78 Tbscl tck tms, tdi Tbsis Tbsih tdo Tbsoh Tbsod Data In Tbsss Tbssh Data Out Tbsdh Tbsdd Tbsch A4772-01 Datasheet ...
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... Tbsoe Tbsde Parameter Minimum Typical 10 – 50 – – 40 – 20 – 40 – 40 – 20 – 5 – 5 – 40 – ® Intel IXP1200 Network Processor Tbsoz Tbsdz A4773-01 Maximum Units Notes MHz – – – ns – – ns – – – ns – – ns – – ...
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... Intel IXP1200 Network Processor 7.3.7 IX Bus 7.3.7.1 FCLK Signal AC Parameter Measurements Figure 19. FCLK Signal AC Parameter Measurements V ptp Table 44. FCLK Signal AC Parameter Measurements Symbol F CLK high 2 T low V ptp Maximum F frequency for 232 MHz rated parts is 104 MHz. Maximum F CLK Maximum F frequency for 166 MHz rated parts is 66 MHz ...
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... Table 46. ® Intel IXP1200 Network Processor T val(min) T off T h A6989-02 Maximum (IX Bus Speed) Unit Condition 104 66 85 104 MHz MHz MHz MHz 7.0 7.0 5. load --- ...
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... Intel IXP1200 Network Processor Table 46. Signal Delay Derating Signal FDATA[63:0] 0.055 FBE#[7:0] 0.055 FPS[2:0] 0.065 TK_REQ_OUT 0.065 TK_REQ_IN 0.065 RDYCTL#[4:0] 0.065 RDYBUS[7:0] 0.065 TXAXIS 0.065 EOP 0.065 SOP 0.065 GPIO[3:0] 0.065 PORTCTL#[3:0] 0.095 TK_OUT 0.095 RXFAIL 0.095 ...
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FCLK MAC0/Rx A PORTCTL#[0] PORTCTL#[1] PORTCTL#[2] PORTCTL#[3] FPS[2:0] Port A FDAT[63:0] Ra0 Ra3 Ra4 Ra5 Ra6 Ra7 Tb0 Ra1 Ra2 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: int_1200_OE is not an IXP1200 signal shown to indicate when the IXP1200 drives ...
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FCLK PORTCTL#[3:0] No Select MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...
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FCLK PORTCTL#[3:0] MAC0/Rx A MAC1/ Select ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# ext_MAC3_Tx# FPS[2:0] Port A Port B FDAT[63:0] Ra1 Ra4 Ra5 Ra6 Ra7 Tb1 Tb2 Tb3 Tb6 Tb7 Ra0 Tb0 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] Int_1200_OE Notes: Signals using prefix "ext_" are ...
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FCLK PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is ...
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FCLK PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is not ...
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FCLK PORTCTL#[3:0] MAC0/ Select ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is ...
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FCLK No Select PORTCTL#[3:0] No Select MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE ...
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FCLK PORTCTL#[3:0] MAC0/ Select ext_MAC0_Rx# ext_MAC1_Tx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is not an ...
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FCLK No Select PORTCTL#[3:0] MAC0/ Sel ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE is not an IXP1200 ...
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FCLK No Select No Select PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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FCLK No PORTCTL#[3:0] MAC0/Rx A Sel ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...
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FCLK No Select PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...
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FCLK No Select PORTCTL#[3:0] MAC0/Rx A ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1200_OE ...
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FCLK No PORTCTL#[3:0] MAC0/Rx A Sel ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# Port A FPS[2:0] FDAT[63: Ra0 Ra1 Ra2 Ra3 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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FCLK No Sel No Sel PORTCTL#[7 :0] MAC0/Rx A MAC1/Rx B ext_MAC0_Rx# ext_MAC1_Rx# FPS[2:0] Port A Fetch-9 FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 Ra8 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an ...
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FCLK No Sel No Sel PORTCTL#[3:0] MAC0/Tx A ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# FPS[2:0] Port A FDAT[63:0] Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...
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FCLK No Sel No Sel PORTCTL#[3:0] MAC0/Tx A ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# FPS[2:0] Port A FDAT[63:0] Ta3 TaP Ta0 Ta1 Ta2 Ta4 Ta5 Ta6 Ta7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...
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FCLK No Sel PORTCTL#[1 :0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port FDAT[31:0] Ra0 Ra1 Ra2 Ra3 Rb0 Rb1 Rb2 Rb3 14 ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# Port A Port B FPS[2: FDAT[31:0] Ra0 Ra1 Rb0 Rb1 14 13 ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port FDAT[31:0] Ra0 Ra1 Ra2 Ra3 RaS 14 13 SOP/SOP_RX EOP/EOP_RX ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# Port A FPS[2:0] Ra FDAT[31:0] Ra0 Ra1 Ra2 Ra3 RaS 13 SOP/SOP_RX EOP/EOP_RX FBE#[3:0] Notes: ...
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FCLK No Sel No Sel PORTCTL#[1:0] MAC0/Rx A MAC1/ used with PORTCTL# RDYCTL#[4]/ 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port A Ra FDAT[31:0] Ra0 Ra1 Ra2 RaS 12 SOP/SOP_RX EOP/EOP_RX FBE#[3:0] Notes: Signals ...
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FCLK No PORTCTL#[1:0] MAC0/Rx A MAC0/Rx B Sel ( used with PORTCTL# RDYCTL#[4] 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# Port A FPS[2: FDAT[31:0] Ra1 Ra0 SOP/SOP_RX EOP/EOP_RX FBE#[3:0] Notes: Signals ...
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FCLK No No PORTCTL#[1:0] MAC0/Rx A MAC1/Rx B Sel Sel ( used with PORTCTL# RDYCTL#[4] 3+ MAC mode only ) FC_EN1#/RXPEN# ext_MAC0_Rx# ext_MAC1_Rx# ext_MAC2_Rx# ext_MAC3_Rx# FPS[2:0] Port A Port FDAT[31:0] Ra0 Ra1 Rb0 Rb1 29 30 ...
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FCLK No Sel No Sel PORTCTL#[3:2] MAC0/Tx A GPIO[0]/ ( used with PORTCTL# FC_EN0#/TXPEN 3+ MAC mode only ) ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# Port A GPIO[3:1] FDAT[31:0] Ta0 Ta1 Ta2 Ta3 Ta15 TK_REQ_OUT/ SOP_TX TK_REQ_IN/ EOP_TX FBE#[7:4] Notes: Signals using prefix ...
Page 108
FCLK No Sel PORTCTL#[3:2] MAC0/Tx A GPIO[0]/ ( used with PORTCTL# FC_EN0#/TXPEN 3+ MAC mode only ) ext_MAC0_Tx# ext_MAC1_Tx# ext_MAC2_Tx# Port A GPIO[3:1] TaP TaP FDAT[31:0] Ta0 Ta1 Ta2 Ta14 Ta15 0 1 TK_REQ_OUT/ SOP_TX TK_REQ_IN/ EOP_TX FBE#[7:4] Notes: Signals ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select - See Footnote* Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=5 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select - 5 clks Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs ...
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FCLK PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select-5 clks ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=5 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder ...
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FastPort request #2 pending FCLK PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC ...
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FCLK No PORTCTL#[3:0] FastPort/Rx Port 0 req#1 Sel ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT = don't care FAST_RX1 int_1200_OE Notes: Signals using prefix "ext_" are outputs of an ...
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FCLK No Sel PORTCTL#[3:0] FastPort/Rx Port 0 req#1 FastPort/Rx Port 1 req#1 ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] register FP_READY_WAIT=0 FAST_RX1 FAST_RX for Port 1 req#1 sampled FAST_RX2 int_1200_OE Notes: ...
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FCLK PORTCTL#[3:0] FastPort/Rx Port 0 req#1 No Select ext_MAC0_Rx# FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP/SOP_RX EOP/EOP_RX FBE#[7:0] FAST_RX for Port 0 req#2 sampled register FP_READY_WAIT=0 FAST_RX1 FAST_RX for Port 1 req#1 sampled- pending ...
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... Figure 56. Consecutive Fetch Ready Flags, 3+ MAC Mode (with External Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK RDYCTL#[4:0] NOP ext_MAC0_RxSel# ext_MAC1_RxSel# ext_MAC2_RxSel# ext_MAC3_RxSel# RDYBUS[7:0] Note: Signals using prefix "ext_" are outputs of an external decoder. Datasheet Intel MAC0/ RxRdy MAC0/ TxRdy MAC1/ TxRdy MAC0/TxRdy Flags MAC1/TxRdy Flags MAC0/RxRdy NOP MAC1/RxRdy ...
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... Intel IXP1200 Network Processor Figure 57. Fetch Ready Flags, Get/Send Commands, 3+ MAC Mode (with External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK MAC0/TxRdy RDYCTL#[3:0] NOP ext_MAC0_TxRdy# RDYBUS[7:0] Note: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. Figure 58. Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready Flags, ...
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... Configuration uses an external Flow Control latch, and an external registered decoder. Signals using prefix "ext_" are outputs of the external registered decoder. Datasheet RxRdyMAC0 RxRdyMAC1 RxRdyMAC2 NOP NOP NOP MAC0/RxRdy Flags MAC1/RxRdy Flags ® Intel IXP1200 Network Processor FlwCtMAC0 NOP NOP MAC2/RxRdy Flags MAC0/Flow Control Mask A7777-01 119 ...
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... TK_OUT #1 (is TK_IN TK_OUT #2 FDAT[63:0] PORTCTL#[7:0] Notes Driven by the Intel if the transfer Driven high for one cycle by the IXP1200 Network Processor #2 (no port is selected), then tristated Weak external pull-up resistors are recommended on PORTCTL#[7:0], FPS[2:0] and TxASIS. 7.3.8 SRAM Interface 7 ...
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... MHz MHz MHz — — — 8.62 4.02 4 3.3 4.02 4 3.3 0.29 0.25 0.21 ® Intel IXP1200 Network Processor Maximum (IXP1200 Core Speed) Unit 166 200 232 MHz MHz MHz 83 100 116 MHz — — — ns — — — ...
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... Intel IXP1200 Network Processor 7.3.8.2 SRAM Bus Signal Timing Figure 62. SRAM Bus Signal Timing SCLK Outputs Inputs Table 48. SRAM Bus Signal Timing Symbol T Clock to data output valid delay val T Clock to control outputs valid delay ctl Data input setup time before SCLKIN for ...
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... Intel IXP1200 Network Processor Minimum Derating (ns/pF) (IX Bus Speed) 100 MHz 116 MHz — — 0.025 0.015 0.025 0.015 0.025 0.015 0.025 0.015 0.025 ...
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... Intel IXP1200 Network Processor 7.3.8.3 SRAM Bus - SRAM Signal Protocol and Timing Figure 63. Pipelined SRAM Read Burst of Eight Longwords SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Figure 64. Pipelined SRAM Write Burst of Eight Longwords SCLK ...
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... SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Note 1: There is always a 1 clock cycle idle state on the data bus when switching from read to write. Datasheet ® Intel IXP1200 Network Processor CE#[3:0] = 1110 CE#[3:0] = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) ...
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... Intel IXP1200 Network Processor Figure 66. Pipelined SRAM Longword Write Followed by 2 Longword Burst Read Followed by 4 Longword Burst Write SCLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Note 1: There is always a one clock cycle idle state on the data bus when switched from a read to write cycle. ...
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... Figure 67. Flowthrough SRAM Read Burst of Eight Longwords SACLK SLOW_EN# SLOW_RD# SLOW_WR# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] A[18:0] SWE# SOE# DQ[31:0] Datasheet ® Intel IXP1200 Network Processor CE#[3:0] = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) A7 D(A7) A7021-02 127 ...
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... Intel IXP1200 Network Processor 7.3.8.4 SRAM Bus - BootROM and SlowPort Timings Timing for the BootROM and SlowPort areas are programmable through the SRAM configuration registers described in the IXP1200 Network Processor Family Microcode Programmer’s Reference Manual. The designer should refer to this manual to understand restrictions in selecting timing values ...
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... SRAM SlowPort Cycle Count (Does not apply to BootROM) BootROM Cycle Count (11) Cyele time= Cycle Count + 1 (12 cycles) 15:8 7 SLOW__EN# Deassert. (3) SLOW_RD#/SLOW_WE# Deassert. (5) SLOW__EN# Assert (10) ® Intel IXP1200 Network Processor Valid Address Valid Data Valid SLOW_EN# Deassert. (3) SLOW_WE# Deassert ...
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... Intel IXP1200 Network Processor Figure 70. Pipelined SRAM Two Longword Burst Read Followed by BootROM Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] SWE# SOE# BootROM_CE#[3:0] 130 A1 A2 D(A1) D(A1) D(A2) CE#<3:0> = 1110 BootROM_CE# = -(-SLOW_EN# & -CE#) ...
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... SRAM Slow Port Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) BootROM Cycle Count (Does not apply to SRAM SlowPort) 15:8 7 SLOW__EN# Deassert. (3) SLOW_RD#/SLOW_WE# Deassert. (5) SLOW__EN# Assert (10) ® Intel IXP1200 Network Processor Valid Address Valid SLOW_EN# Deassert. (3) SLOW_RD# Deassert. (5) ...
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... Intel IXP1200 Network Processor Figure 72. SRAM SlowPort Write A[18:0] DQ[31:0] SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# SP_CE# Externally Generated Signal SRAM SlowPort Chip select signal - SP_CE# & address Cycle Count = Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 ...
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... SRAM_SLOW_CONFIG=000A:0B0Fh where RDY# Pause State=Ah, BCC=0Bh, and SCC=0Fh SRAM_SLOWPORT_CONFIG=0D0E:0501h where SRWA=0Dh, SCEA=0Eh, SRWD=05h, SCED=01 SRAM_CSR=0009:4810h where <19>=1, RDY# enabled Datasheet RDY# input sampled asynchronously while waiting in internal pause state A RDY# pause state=Ah load count ® Intel IXP1200 Network Processor 2 SCLKs Minimum RDY#_Pause_State value= additional (SRWD+5) minimum wait states ...
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... Intel IXP1200 Network Processor Figure 74. Pipelined SRAM Two Longword Burst Read Followed By SlowPort Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] SP_CE# SLOW_EN# SLOW_RD# SLOW_WE# HIGH_EN#/RDY# LOW_EN#/DIRW# CE#[3:0] SWE# SOE# BootROM_CE#[3:0] 134 D(A1) D(A2) D(A3) CE#[3:0] = 1110 A3 D(A3) D(A3) ...
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... MHz MHz MHz — — — 8.62 4.02 4 3.3 4.02 4 3.3 0.29 0.25 0.21 ® Intel IXP1200 Network Processor A6992-01 Maximum (IXP1200 Core Speed) Unit 166 200 232 MHz MHz MHz 83 100 116 MHz — — — ns — — ...
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... Intel IXP1200 Network Processor 7.3.9.2 SDRAM Bus Signal Timing Figure 76. SDRAM Bus Signal Timing Control Outputs (RAS#, CAS#, WE#, DQM, MADR) Table 51. SDRAM Bus Signal Timing Parameters Symbol T Clock to data output valid delay val T SDCLK to control output valid delay ctl T Data input setup time before SDCLK ...
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... Intel IXP1200 Network Processor Minimum Derating (ns/pF) (IX Bus Speed) 100 MHz 116 MHz — — 0.025 0.015 0.025 0.015 0.025 0.015 0.025 0.015 0.025 ...
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... Intel IXP1200 Network Processor altogether, and simply have this time be the sum of tRP and tRASmin, as discussed above. The IXP1200 Network Processor Family Microcode Programmer’s Reference Manual refers to this as the tRC Bank Cycle Time. Also referred to as “ACTIVE to ACTIVE command period” in SDRAM datasheets ...
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... SDRAM programmable register value. In actual use, refresh cycles will not occur immediately after tRSC cycles due to SDRAM unit internal pipeline delays. Datasheet INIT_DLY tRP tRSC Precharge Mode Register all banks Set Command (see note 2) ® Intel IXP1200 Network Processor tRc Auto Auto Refresh Refresh (see note 1) A7009-01 139 ...
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... Intel IXP1200 Network Processor Figure 78. SDRAM Read Cycle SDCLK RAS# CAS# WE# MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL programmed in SDRAM_MEMCTL0 Figure 79. SDRAM Write Cycle SDCLK ...
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... Are asynchronous relative to any device outside the IXP1200. Datasheet tRASmin tRCD tDQZ DQM remains high Activate Read during modify command command ® Intel IXP1200 Network Processor tDPL tRWT Write DQM remains high command until next read or write command Precharge command A7010-01 ...
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... Mechanical Specifications 8.1 Package Dimensions The IXP1200 is contained in a 432-HL-PBGA package, as shown in the following illustrations. Figure 81. IXP1200 Part Marking Pin 1 142 i GCIXP1200XX FPO# INTEL(M)(C)2001 XXXXXXXXXXX xxxxxxxSz YYWW Product Name FPO # Copyright Info Country of Origin Alt# and Date Code A8454-02 Datasheet ...
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... Figure 82. 432-Pin HL-BGA Package - Bottom View 0. Figure 83. IXP1200 Side View Figure 84. IXP1200 A-A Section View Datasheet ® Intel IXP1200 Network Processor A 1 Ball Corner A7063-02 bbb C ccc aaa –C– Seating Plane A7064-01 P ddd A7043-01 143 ...
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... Intel IXP1200 Network Processor 8.2 IXP1200 Package Dimensions (mm) Table 53. IXP1200 Package Dimensions (mm) Symbol A Overall thickness A Ball height 1 A Body thickness 2 D Body size D Ball footprint 1 E Body size E Ball footprint 1 b Ball diameter aaa Coplanarity bbb Parallel ccc Top flatness ...