MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 157

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that
indicate the result of a processor operation. Table 5-3 lists the effect of each instruction on
these bits. The carry bit and the multiprecision extend bit are separate in the M68000
Family to simplify programming techniques that use them. Refer to Table 5-7 as an
example.
5-20
ABCD
ADD, ADDI, ADDQ
ADDX
AND, ANDI, EOR, EORI,
MOVEQ, MOVE, OR,
ORI, CLR, EXT, NOT,
TAS, TST
CHK
CHK2, CMP2
SUB, SUBI, SUBQ
SUBX
CMP, CMPI, CMPM
DIVS, DIVU
MULS, MULU
SBCD, NBCD
NEG
NEGX
ASL
ASL (r = 0)
LSL, ROXL
LSR (r = 0)
ROXL (r = 0)
ROL
ROL (r = 0)
ASR, LSR, ROXR
ASR, LSR (r = 0)
ROXR (r = 0)
Operations
Table 5-3. Condition Code Computations
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MC68340 USER’S MANUAL
Go to: www.freescale.com
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Z
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V
U
U
U
U
0
0
0
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0
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0
0
0
0
0
0
C
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C = X
C = X
C = Decimal Carry
Z = Z
V = Sm
C = Sm
V = Sm
C = Sm
Z = Z
Z = (R = LB) V R = UB
C = (LB < UB)
V = S
C = Sm
V = S
C = Sm
Z = Z
V = S
C = Sm
V = Division Overflow
V = Multiplication Overflow
C = Decimal Borrow
Z = Z
V = Dm
C = Dm V Rm
V = Dm
C = Dm V Rm
Z = Z
V = Dm
C = D – r + 1
C = Dm – r + 1
C = Dm – r + 1
C = Dr – 1
(Dm–1 V
UB < LB)
R
R
R
R
R
Dm
Dm
Dm
Dm
Dm
Dm V R
Dm V R
D V Rm
D V Rm
D V Rm
Rm
Rm
( D – 1 V
Special Definition
R V Sm
R V Sm
R V Sm
+ Dm – r)
R V S
R V S
R0
(IR < LB) V R > UB) V
(R > UB)
R0
R0
R0
R0
Dm V Sm
D V Sm
D V Sm
D V Sm
Dm V Sm
V D – r ) V D
D
D
D
D
D
(R < LB)
Rm
Rm
Rm
Rm
Rm
Rm
Rm
Rm
R
R
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