MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 87

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

3.5.3 Halt Operation
When HALT is asserted and BERR is not asserted, the MC68340 halts external bus
activity at the next bus cycle boundary (see Figure 3-21). HALT by itself does not
terminate a bus cycle. Negating and reasserting HALT in accordance with the correct
timing requirements provides a single-step (bus cycle to bus cycle) operation. Since HALT
affects external bus cycles only, a program that does not require use of the external bus
may continue executing. The single-cycle mode allows the user to proceed through (and
debug) external MC68340 operations, one bus cycle at a time. Since the occurrence of a
bus error while HALT is asserted causes a retry operation, the user must anticipate retry
cycles while debugging in the single-cycle mode. The single-step operation and the
software trace capability allow the system debugger to trace single bus cycles, single
instructions, or changes in program flow.
When the MC68340 completes a bus cycle with HALT asserted, D15–D0 is placed in the
high-impedance state, and bus control signals are negated (not high-impedance state);
the A31–A0, FCx, SIZx, and R/ W signals remain in the same state. The halt operation has
no effect on bus arbitration (see 3.6 Bus Arbitration). When bus arbitration occurs while
the MC68340 is halted, the address and control signals are also placed in the high-
impedance state. Once bus mastership is returned to the MC68340, if HALT is still
3-38
FC3–FC0
D15–D10
CLKOUT
DSACKx
A31–A0
BERR
HALT
R/W
AS
DS
Freescale Semiconductor, Inc.
S0
For More Information On This Product,
Figure 3-20. Late Retry Sequence
S2
WRITE
CYCLE
MC68340 USER’S MANUAL
Go to: www.freescale.com
S4
HALT
S0
S2
RERUN
WRITE
S4
MOTOROLA