MPC8347EVVAJDB Freescale Semiconductor, MPC8347EVVAJDB Datasheet - Page 76

• Manufacturer Part Number: MPC8347EVVAJDB
• Description: IC MPU PWRQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVAJDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Clocking
19 Clocking
Figure 41
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8347E is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8347E to function. When the
MPC8347E is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN
signal should be tied to GND.
76
CFG_CLKIN_DIV
shows the internal distribution of the clocks.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
CLKIN
MPC8347E
System PLL
Figure 41. MPC8347E Clock Subsystem
e300 Core
PCI Clock
csb_clk
Clock
Divider
Unit
csb_clk to Rest
of the Device
ddr_clk
lbiu_clk
Core PLL
To Local Bus
Controller
Memory
Controller
To DDR
Memory
Clock
LBIU
DDR
/n
DLL
Div
/2
core_clk
6
6
5
MCK[0:5]
MCK[0:5]
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
PCI_SYNC_OUT
PCI_CLK_OUT[0:4]
PCI_CLK/
PCI_SYNC_IN
Freescale Semiconductor
DDR
Memory
Device
Local Bus
Memory
Device