GCIXP1200GA Intel, GCIXP1200GA Datasheet - Page 15

• Manufacturer Part Number: GCIXP1200GA
• Description: IC MPU NETWORK 166MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GA

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 166MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839427

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Specification Update
Data Transfers on Multiword PCI Target Read and DMA Transfers
On a multiword PCI target read, or on DMA Channel Descriptor reads from SDRAM, the data read
from SDRAM may be incorrect. These results have been observed under conditions of high
SDRAM utilization.
A Multiword PCI Target read operation may fail with the first longword transfer being correct and
the possibility of subsequent transfers returning incorrect data from SDRAM. A DMA operation by
the StrongARM* core or Microengines may fail as the DMA Descriptor information may be
incorrectly fetched from SDRAM causing data to be read or written at an incorrect address. It is
possible that even if the Descriptor is correctly fetched on a DMA read, the read data transfer may
return incorrect data.
Limit PCI reads to only one longword per request and avoid the use of DMA operations.
Fixed
PCI Performance
The PCI is not likely to run consistently at 66 MHz. The current estimate of the supported speed is
60 MHz. This will be confirmed once the first sample lot is characterized and if necessary, will be
fixed in the next pass.
PCI devices may be limited to a maximum frequency of 60 MHz.
Run the PCI Bus at 33 MHz or 60 MHz.
Fixed
Packet Status Length
When the IX Bus is configured in 32-bit unidirectional mode with a packet status length of 64 bits,
the status may be received in error.
Using 64-bit status in 32-bit unidirectional IX Bus mode can have unpredictable results.
Use a packet status length of only 32 bits (set bit 26 in the RCV_REQ register to 0).
Fixed
Clock Setup Time
Because the SRAM and SDRAM setup times are directly related to the loading of SCLK and
SDCLK, excessive setup times (T
value of T
Inability to meet the data setup time specification for memory devices.
Buffer SCLK and SDCLK with a zero skew clock buffer such as a Cypress CY2309.
NoFix
su
for both memory interfaces is 7.5 ns.
su
) may be seen under heavy loading conditions. The maximum
Intel
®
IXP1200 Network Processor
Errata
15