GCIXP1200GA Intel, GCIXP1200GA Datasheet - Page 26

• Manufacturer Part Number: GCIXP1200GA
• Description: IC MPU NETWORK 166MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GA

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 166MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839427

Intel
Errata
26
®
IXP1200 Network Processor
Workarounds depend on the register affected:
Status (PCI_CMD_STAT), StrongARM* Core Control (SA_CONTROL)
W1C bits are normally used for bits that are set by asynchronous events that must be acknowledged
by the StrongARM* core, and cleared to denote that acknowledgement. The problem with the
write/verify workaround is the case when the write clears the bit, and then the bit gets set again
before the read happens. The compare would assume the write did not happen (because the W1C
bit is set) and then write again, thereby losing the second event. Doing the write/verify operation
atomically (meaning with interrupts disabled) shortens the interval of vulnerability, but does not
guarantee perfect operation.
Doorbell PCI Mask (DBELL_PCI_MASK)
Doorbell SA Mask (DBELL_SA_MASK)
IRQ_Status (IRQ_STATUS)
IRQ_Raw_Status (IRQ_RAW_STATUS)
IRQ_Enable (IRQ_ENABLE)
IRQ_Enable_Set (IRQ_ENABLE_SET)
IRQ_Enable_Clear (IRQ_ENABLE_CLEAR)
IRQ_Soft (IRQ_SOFT)
FIQ_Status (FIQ_STATUS)
FIQ_Raw_Status (FIQ_RAW_STATUS)
FIQ_Enable (FIQ_ENABLE)
FIQ_Enable_Set (FIQ_ENABLE_SET)
FIQ_Enable_Clear (FIQ_ENABLE_CLEAR)
FIQ_Soft (FIQ_SOFT)
Timer 1 Load (TIMER_1_LOAD)
Timer 1 Value (TIMER_1_VALUE)
Timer 1 Control (TIMER_1_CONTROL)
Timer 1 Clear (TIMER_1_CLEAR)
Timer 2 Load (TIMER_2_LOAD)
Timer 2 Value (TIMER_2_VALUE)
Timer 2 Control (TIMER_2_CONTROL)
Timer 2 Clear (TIMER_2_CLEAR)
Timer 3 Load (TIMER_3_LOAD)
Timer 3 Value (TIMER_3_VALUE)
Timer 3 Control (TIMER_3_CONTROL)
Timer 3 Clear (TIMER_3_CLEAR)
Timer 4 Load (TIMER_4_LOAD)
Timer 4 Value (TIMER_4VALUE)
Timer 4 Control (TIMER_4_CONTROL)
Timer 4 Clear (TIMER_4_CLEAR)
Register Name
150
154
180
184
188
188
18c
190
280
284
288
288
28c
290
300
304
308
30c
320
324
328
32c
340
344
348
34c
360
364
368
36c
Offset
RW
RW
RO
RO
RO
W1S
W1C
RW
RO
RO
RO
W1S
W1C
RW
RW
RO
RW
WO
RW
RO
RW
WO
RW
RO
RW
WO
RW
RO
RW
WO
Type
Specification Update
N
N
N
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
N
Y
N
N
N
Y
N
N
N
Y
N
N
N
Y
Side Effects