W681310SG Nuvoton Technology Corporation of America, W681310SG Datasheet - Page 12

• Manufacturer Part Number: W681310SG
• Description: IC VOICEBAND CODEC 3V 1CH 20SOP
• Manufacturer: Nuvoton Technology Corporation of America
• Type: PCMr

Specifications of W681310SG

• Data Interface: PCM Audio Interface
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 2.7 V ~ 5.25 V
• Voltage - Supply, Digital: 2.7 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOP
• For Use With: W681360DK - KIT DEVELOPMENT FOR W681360
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is held
HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync
pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 sec.
During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low
impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted.
The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes
LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will
determine whether the next frame sync is a long or a short frame sync, based on the previous frame
sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after
every power down state. More detailed timing information can be found in the interface timing section.
The W681310 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH
for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the
bit-clock, the W681310 starts clocking out the data on the PCMT pin, which will also change from high to
low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway the
LSB. The Short Frame Sync operation of the W681310 is based on an 8-bit data word. When receiving
data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides
with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a
long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT
pin will be high impedance for two frame sync cycles after every power down state. More detailed timing
information can be found in the interface timing section.
The GCI interface mode is selected when the BCLKR pin is connected to V
cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface consists of 4
pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects channel B1 or B2
for transmit and receive. Data transitions occur on the positive edges of the data clock DCL. The Frame
Sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is running half
the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively. Therefore, channel
B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles
of DCL. For more timing information, see the timing section. The GCI interface supports bit clocks of 512
kHz to 6176 kHz for data rates of 256 kHz to 3088 kHz.
The IDL interface mode is selected when the BCLKR pin is connected to V
cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4
pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects
channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first positive
edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle long. The
data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC
pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC
pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL
SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data
transmission and also in the time slot of the unused channel. For more timing information, see the timing
section.
7.4.2. Short Frame Sync
7.4.3. General Circuit Interface (GCI)
7.4.4. Interchip Digital Link (IDL)
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Publication Release Date: January 2011
DD
SS
for two or more frame sync
for two or more frame sync
W681310
Revision B17