CY7C63823-SXC Cypress Semiconductor Corp, CY7C63823-SXC Datasheet - Page 37

• Manufacturer Part Number: CY7C63823-SXC
• Description: IC USB PERIPHERAL CTRLR 24-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63823-SXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• No. Of I/o's: 20
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: PS/2, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 14-1. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
Table 14-2. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Document 38-08035 Rev. *N
This pin is shared between the P0.0 GPIO use and the CLKIN pin for an external clock. When the external clock input is enabled
(Bit[0] in register CPUCLKCR Table 10-3 on page 23) the settings of this register are ignored.
The use of the pin as the P0.0 GPIO is available in all the enCoRe II parts.
This pin is shared between the P0.1 GPIO use and the CLKOUT pin. When CLK output is set, the internally selected clock is
sent out onto P0.1CLKOUT pin.
The use of the pin as the P0.1 GPIO is available in all the enCoRe II parts.
Bit 7: CLK Output
0 = The clock output is disabled.
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
Pull-Up Enable
TTL Threshold
Output Enable
Open Drain
3.3V Drive
High Sink
Port Data
Data In
CLK Output
Reserved
R/W
7
–
0
7
0
Int Enable
Int Enable
R/W
R/W
6
0
6
0
Int Act Low
Int Act Low
Figure 14-1. Block Diagram of a GPIO
R/W
R/W
5
0
5
0
TTL Thresh
TTL Thresh
VREG
VREG GND
R/W
R/W
4
0
4
0
Reserved
Reserved
3
–
0
3
–
0
(Table 10-1 on page
VREG
V
V
Open Drain
Open Drain
CC
CC
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
GND
R
UP
Pull-up Enable
Pull-up Enable
27) is driven out to the pin.
R/W
R/W
1
0
1
0
GPIO
V
PIN
CC
Output Enable
Output Enable
Data Out
Page 37 of 86
R/W
R/W
0
0
0
0
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