CY7C63823-SXC Cypress Semiconductor Corp, CY7C63823-SXC Datasheet - Page 66

• Manufacturer Part Number: CY7C63823-SXC
• Description: IC USB PERIPHERAL CTRLR 24-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63823-SXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• No. Of I/o's: 20
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Supply Voltage Range: 4V To 5.5V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: PS/2, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24. Register Summary
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Document 38-08035 Rev. *N
58–5F
50–57
60–67
Addr
DA
DB
DC
DE
DF
2A
2B
2C
3C
3D
E1
30
31
32
34
36
39
40
41
42
43
44
45
46
73
74
ITMRCLKCR
OSCLCKCR
CPUCLKCR
TCAPINTE
TCAPINTS
EP0MODE
EP1MODE
EP2MODE
INT_MSK3
INT_MSK2
INT_MSK1
LPOSCTR
INT_CLR0
INT_CLR1
INT_CLR2
CLKIOCR
EP0DATA
EP1DATA
EP2DATA
VREGCR
SPIDATA
USBXCR
EP0CNT
EP1CNT
EP2CNT
IOSCTR
TMRCR
USBCR
SPICR
Name
GPIO Port
ENSWINT
First Edge
Int Enable
Reserved
Reserved Reserved GPIO Port
Reserved Reserved GPIO Port
32 kHz
Enable
Pull-up
Enable
TCAP0
TCAP0
Toggle
Toggle
Toggle
TCAPCLK Divider
Power
Setup
Swap
Hold
USB
Data
Data
Data
rcv’d
USB
Low
Stall
Stall
7
1
foffset[2:0]
Data Valid
Data Valid
Data Valid
Int Enable
Reserved
Reserved 32 kHz Bias Trim [1:0]
Reserved
Reserved
LSB First
Disable
IN rcv’d
Interval
Interval
CLK/2
Sleep
Timer
Timer
Timer
USB
Prog
Prog
(continued)
6
8-bit capture Prescale
Reserved
Reserved
Int Enable
Int Enable
OUT rcv’d ACK’d trans
USB CLK
NAK Int
NAK Int
Enable
Enable
Select
Timer
Timer
INT1
1-ms
1-ms
TCAPCLK Select
5
3
3
Comm Mode
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO Port 2 PS/2 Data
GPIO Port 2
USB Active USB Reset
USB Active
Ack’d trans
Ack’d trans
Endpoint 0 Data Buffer [7:0]
Endpoint 1 Data Buffer [7:0]
Endpoint 2 Data Buffer [7:0]
GPIO Port
Int Enable
Int Enable
4
0
SPIData[7:0]
Reserved
Device Address[6:0]
USB Reset
Cap0 16bit
PS/2 Data
Int Enable
Cap1 Fall
Cap1 Fall
Reserved
Receive
Enable
Low Int
Enable
Reserved
Active
Active
CPOL
Low
ITMRCLK Divider
SPI
3
Reserved
SPI Transmit
Cap1 Rise
Cap1 Rise
32 kHz Freq Trim [3:0]
Gain[4:0]
Int Enable
Int Enable
USB EP2
USB EP2
CPHA
Active
Active
INT2
INT2
Byte Count[3:0]
Byte Count[3:0]
Byte Count[3:0]
2
Mode[3:0]
Mode[3:0]
Mode[3:0]
Reserved
Keep Alive
Fine Tune
Int Enable
Int Enable
Cap0 Fall
Cap0 Fall
USB EP1
USB EP1
Counter
Counter
Active
Active
16-bit
Wrap
16-bit
Wrap
Only
INT0
ITMRCLK Select
CLKOUT Select
1
SCLK Select
CLK Select
USB Force
Cap0 Rise
Cap0 Rise
Int Enable
Int Enable
POR/LVD
USB EP0
USB EP0
Osclock
Disable
TCAP1
TCAP1
Enable
Active
Active
VREG
CY7C63310, CY7C638xx
CPU
State
USB
0
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
b-bbbbbb
ccccbbbb
b-bcbbbb
b-bcbbbb
-bbbbbbb
-bbbbbbb
bbbbb---
---bbbbb
----bbbb
----bbbb
-bb----b
------bb
------bb
b------b
b-------
R/W
00000000
00000000
00000000
00010000
00000000
000ddddd
dddddddd
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
????????
????????
????????
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
10001111
Default
Page 66 of 86
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