TDA8024T/C1,118 NXP Semiconductors, TDA8024T/C1,118 Datasheet - Page 10

• Manufacturer Part Number: TDA8024T/C1,118
• Description: IC SMART CARD INTERFACE 28-SOIC
• Manufacturer: NXP Semiconductors

Specifications of TDA8024T/C1,118

• Package / Case: 28-SOIC (7.5mm Width)
• Controller Type: Smart Card Interface
• Interface: Analog
• Voltage - Supply: 2.7 V ~ 6.5 V
• Current - Supply: 1.5mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 25 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935271342118; TDA8024TD-T; TDA8024TD-T

Philips Semiconductors
8.3
The card clock signal (CLK) is derived from a clock signal
input to pin XTAL1 or from a crystal operating at up to
26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be f
or
inputs CLKDIV1 and CLKDIV2 (see Table 1).
Table 1 Clock frequency selection; note 1
Note
1. The status of pins CLKDIV1 and CLKDIV2 must not be
The frequency change is synchronous, which means that
during transition no pulse is shorter than 45% of the
smallest period, and that the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change is
effective for only eight periods of XTAL1 after the
command.
The duty factor of f
pin XTAL1.
In order to reach a 45 to 55% duty factor on pin CLK, the
input signal on pin XTAL1 should have a duty factor of
48 to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be
45 to 55% depending on the circuit layout and on the
crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.
2004 July 12
IC card interface
1
/
changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of
any state of CLK is eight periods of XTAL1.
8
CLKDIV1
Clock circuitry
f
XTAL
0
0
1
1
. Frequency selection is made via
XTAL
depends on the signal present at
CLKDIV2
0
1
1
0
XTAL
,
1
/
2
f
XTAL
,
f
------------ -
f
------------ -
f
------------ -
1
f
f
XTAL
XTAL
XTAL
XTAL
/
CLK
4
8
4
2
f
XTAL
10
The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
pin XTAL1 is permanent, the clock pulse is applied to the
card as shown in the activation sequences shown in Figs 7
and 8.
If the signal applied to XTAL1 is controlled by the system
microcontroller, the clock pulse will be applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
8.4
The three data lines I/O, AUX1 and AUX2 are identical.
The idle state is realized by both I/O and I/OUC lines being
pulled HIGH via a 11 k resistor (I/O to V
V
Pin I/O is referenced to V
allowing operation when V
The first side of the transceiver to receive a falling edge
becomes the master. An anti-latch circuit disables the
detection of falling edges on the line of the other side,
which then becomes a slave.
After a time delay t
is turned on, thus transmitting the logic 0 present on the
master side.
When the master side returns to logic 1, a P transistor on
the slave side is turned on during the time delay t
then both sides return to their idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions; as shown in Fig.6, it is able to deliver more than
1 mA at an output voltage of up to 0.9V
load. At the end of the active pull-up pulse, the output
voltage depends only on the internal pull-up resistor and
the load current.
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
DD
).
I/O transceivers
d(edge)
, an N transistor on the slave side
CC
CC
, and pin I/OUC to V
is not equal to V
Product specification
CC
TDA8024
CC
into an 80 pF
and I/OUC to
DD
DD
.
pu
, thus
and