UPD720101F1-EA8-A Renesas Electronics America, UPD720101F1-EA8-A Datasheet - Page 22

• Manufacturer Part Number: UPD720101F1-EA8-A
• Description: HOST CTLR USB 2.0 144-FBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD720101F1-EA8-A

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 972-1002

Power consumption
20
Notes 1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend
Power Consumption
Remark These are estimated value on Windows™ XP environment.
Parameter
2. The number of active ports is set by the value of Port No Field in PCI configuration space EXT register.
3. This is the case when PCI bus state is B0.
4. This is the case when PCI bus state is B3.
on the number of active ports.
Symbol
P
P
P
P
P
P
P
P
P
P
WD0-0
WD0-2
WD0-3
WD0-4
WD0-5
WD0_C
WD1
WD2
WD3H
WD3C
Device state = D0, All the ports does not connect to
any function, and each OHCI controller is under
UsbSuspend and EHCI controller is stopped.
The power consumption under the state without
suspend. Device state = D0, The number of active
ports is 2.
The power consumption under the state without
suspend. Device state = D0, The number of active
ports is 3.
The power consumption under the state without
suspend. Device state = D0, The number of active
ports is 4.
The power consumption under the state without
suspend. Device state = D0, The number of active
ports is 5.
The power consumption under suspend state during
PCI clock is stopped by CRUN0. Device state = D0.
Device state = D1, Analog PLL output is stopped.
Device state = D2, Analog PLL output is stopped.
Device state = D3
output is stopped.
Device state = D3
High-speed device(s) is (are) on the port.
High-speed device(s) is (are) on the port.
High-speed device(s) is (are) on the port.
High-speed device(s) is (are) on the port.
Full- or low-speed device(s) is (are) on the port.
Full- or low-speed device(s) is (are) on the port.
Full- or low-speed device(s) is (are) on the port.
Full- or low-speed device(s) is (are) on the port.
Note2
Note2
Note2
Note2
Data Sheet S16265EJ5V0DS
hot
cold
Note 3
, VCCRST0 = High, Analog PLL
, VCCRST0 = Low.
Condition
Note 4
Note1
Note 3
Note 3
(30 MHz X’tal)
204.6
253.8
301.6
349.1
Typ.
31.4
53.1
55.3
57.4
59.8
30.5
0.03
7.7
7.7
7.7
(48 MHz OSC)
204.2
255.5
300.1
345.2
Typ.
10.4
31.9
34.2
36.7
38.8
10.4
10.4
10.4
10.4
3.81
µ
PD720101
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA