UPD720101F1-EA8-A Renesas Electronics America, UPD720101F1-EA8-A Datasheet - Page 26

• Manufacturer Part Number: UPD720101F1-EA8-A
• Description: HOST CTLR USB 2.0 144-FBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD720101F1-EA8-A

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 972-1002

24
High-speed Source Electrical Characteristics
Rise time (10 to 90%)
Fall time (90 to 10%)
Driver waveform
High-speed data rate
Microframe interval
Consecutive microframe interval difference
Data source jitter
Receiver jitter tolerance
Hub Event Timings
Time to detect a downstream facing port
connect event
Time to detect a disconnect event at a
hub’s downstream facing port
Duration of driving resume to a
downstream port
Time from detecting downstream resume
to rebroadcast
Inter-packet delay for packets traveling in
same direction for high-speed
Inter-packet delay for packets traveling in
opposite direction for high-speed
Inter-packet delay for root hub response for
high-speed
Time for which a Chirp J or Chirp K must
be continuously detected during reset
handshake
Time after end of device Chirp K by which
hub must start driving first Chirp K
Time for which each individual Chirp J or
Chirp K in the chirp sequence is driven
downstream during reset
Time before end of reset by which a hub
must end its downstream chirp sequence
Parameter
t
t
See Figure 3-6.
t
t
t
See Figure 3-6.
See Figure 3-4.
t
t
t
t
t
t
t
t
t
t
t
HSR
HSF
HSDRAT
HSFRAM
HSRFI
DCNN
DDIS
DRSMDN
URSM
HSIPDSD
HSIPDOD
HSRSPIPD1
FILT
WTDCH
DCHBIT
DCHSE0
Symbol
Data Sheet S16265EJ5V0DS
Nominal
Conditions
124.9375
479.760
Min.
500
500
100
2.5
2.0
2.5
20
88
40
8
125.0625
480.240
4 high-
speed
Max.
2000
192
100
500
2.5
1.0
60
µ
PD720101
Mbps
times
times
times
times
Unit
ms
ms
Bit
Bit
Bit
Bit
ps
ps
µ
µ
µ
µ
µ
µ
µ
(2/2)
s
s
s
s
s
s
s