DS21FT42 Maxim Integrated Products, DS21FT42 Datasheet - Page 76

• Manufacturer Part Number: DS21FT42
• Description: IC FRAMER T1 4X3 12CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FT42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 225mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

will automatically look for 5 ones in a row, followed by a zero. If it finds such a pattern, it will
automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero,
the zero is not removed. The CCR2.0 bit should always be set to a one when the DS21Q42 is extracting
the FDL. More on how to use the DS21Q42 in FDL applications in this legacy support mode is covered
in a separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)
RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RMTCH1/RMTCH2), SR2.2 will be set to a one and the INT* will go active if enabled via IMR2.2.
19.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full 8 bits has been shifted out, the framer will signal the host microcontroller
that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one. The INT* will
also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the
TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer also contains
a zero stuffer, which is controlled via the CCR2.4 bit.
communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing
flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically
look for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones.
RMFDL7
RFDL7
(MSB)
(MSB)
SYMBOL
SYMBOL
RMFDL7
RMFDL0
RFDL7
RFDL0
RMFDL6
RFDL6
POSITION
POSITION
RMTCH1.7
RMTCH2.7
RMTCH1.0
RMTCH2.0
RFDL.7
RFDL.0
RMFDL5
RFDL5
RMFDL4
NAME AND DESCRIPTION
NAME AND DESCRIPTION
MSB of the FDL Match Code
LSB of the FDL Match Code
MSB of the Received FDL Code
LSB of the Received FDL Code
RFDL4
76 of 114
RMFDL3
RFDL3
In both ANSI T1.403 and TR54016,
RMFDL2
RFDL2
RMFDL1
RFDL1
RMFDL0
(LSB)
RFDL0
(LSB)