CY7C68034-56BAXC Cypress Semiconductor Corp, CY7C68034-56BAXC Datasheet - Page 3

• Manufacturer Part Number: CY7C68034-56BAXC
• Description: IC USB NX2LP NAND CNTRLR 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56BAXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
Functional Overview
USB Signaling Speed
NX2LP-Flex operates at two of the three rates defined in the
USB Specification Revision 2.0, dated April 27, 2000:
NX2LP-Flex does not support the low-speed signaling mode
of 1.5 Mbps.
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps.
NAND-Based
NAND-Based
Audio / Video I/O
Figure 1. Example DVB Block Diagram
Figure 2. Example GPS Block Diagram
LCD
GPS Unit
LCD
DVB Unit
D+/-
D+/-
I/O
I/O
NX2LP-
Buttons
Decoder
NX2LP-
Buttons
GPS
Flex
Flex
DVB
CE[7:0]
CE[7:0]
CTL
CTL
I/O
I/O
NAND Bank(s)
NAND Bank(s)
8051 Microprocessor
The 8051 microprocessor embedded in the NX2LP-Flex has
256 bytes of register RAM, an expanded interrupt system and
three timer/counters.
8051 Clock Frequency
NX2LP-Flex has an on-chip oscillator circuit that uses an
external 24-MHz (±100-ppm) crystal with the following charac-
teristics:
An on-chip PLL multiplies the 24-MHz oscillator up to
480 MHz, as required by the transceiver/PHY, and internal
counters divide it down for use as the 8051 clock. The default
8051 clock frequency is 12 MHz. The clock frequency of the
8051 can be changed by the 8051 through the CPUCS
register, dynamically
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical NX2LP-Flex functions. These SFR additions
are shown in Table 1. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with ‘0’
and ‘8’ contain bit-addressable registers. The four I/O ports
A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in NX2LP-Flex.
Because of the faster and more efficient SFR addressing, the
NX2LP-Flex I/O ports are not addressable in external RAM
space (using the MOVX instruction).
I
NX2LP supports the I
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I
device is connected. The I
only available for use after the initial NAND access.
2
• Parallel resonant
• Fundamental mode
• 500-μW drive level
• 12-pF (5% tolerance) load capacitors.
C Bus
12-pF capacitor values assumes a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
Figure 3. Crystal Configuration.
12 pf
C1
CY7C68033/CY7C68034
2
C bus as a master only at 100-/400-kHz.
20 × PLL
24 MHz
2
C bus is disabled at startup and
12 pf
C2
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