CY7C68034-56BAXC Cypress Semiconductor Corp, CY7C68034-56BAXC Datasheet - Page 8

• Manufacturer Part Number: CY7C68034-56BAXC
• Description: IC USB NX2LP NAND CNTRLR 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56BAXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Table 5. Reset Timing Values
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external logic, the oscil-
lator restarts, after the PLL stabilizes, and then the 8051
receives a wakeup interrupt. This applies whether or not
NX2LP-Flex is connected to the USB.
The NX2LP-Flex exits the power-down (USB suspend) state
using one of the following methods:
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is, by default, active LOW.
Program/Data RAM
Internal ROM/RAM Size
The NX2LP-Flex has 1 kBytes ROM and 15 kBytes of internal
program/data RAM, where PSEN#/RD# signals are internally
ORed to allow the 8051 to access it as both program and data
memory. No USB control registers appear in this space.
Internal Code Memory
This mode implements the internal block of RAM (starting at
0x0500) as combined code and data memory, as shown in
Figure 6, below.
Only the internal and scratch pad RAM spaces have the
following access:
Power-on Reset with crystal
Power-on Reset with external
clock source
Powered Reset
• USB bus activity (if D+/D– lines are left floating, noise on
• External logic asserts the WAKEUP pin
• External logic asserts the PA3/WU2 pin.
• USB download (only supported by the Cypress Manufac-
• Setup data pointer
• NAND boot access.
these lines may indicate activity to the NX2LP-Flex and
initiate a wakeup).
turing Tool)
Condition
200 μs + Clock stability time
T
200 μs
5 ms
RESET
Register Addresses
Figure 7. Internal Register Addresses
Figure 6. Internal Code Memory
FFFF
F000
EFFF
E800
E1FF
E7FF
E7C0
E780
E740
E700
E6FF
E500
E4FF
E47F
E400
E3FF
E000
E7BF
E77F
E73F
E480
E200
*SUDPTR, USB download, NAND boot access
FFFF
E200
E1FF
E000
3FFF
0500
0000
CY7C68033/CY7C68034
128 bytes GPIF Waveforms
8051 Addressable Registers
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
2 KBytes RESERVED
Reserved (512)
512 Bytes RAM Data
4 KBytes EP2-EP8
64 Bytes EP1OUT
Reserved (128)
64 Bytes EP1IN
8051 xdata RAM
15 kBytes RAM
Code and Data
USB registers
(PSEN#, RD#,
and 4 kBytes
(RD#, WR#)*
512 bytes
FIFO buffers
(RD#, WR#)
1 kbyte ROM
(8 x 512)
7.5 kBytes
buffers
(512)
WR#)*
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