PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 87

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.5.2
The operation of the Synchronous Master and Slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in Slave mode.
If receive is enabled, by setting bit CREN, prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
 2003 Microchip Technology Inc.
Address
0Ch
18h
19h
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Enable the synchronous master serial port by
PIR1
RCSTA
TXREG USART Transmit Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
USART SYNCHRONOUS SLAVE
RECEPTION
Name
Name
SPEN
CSRC
CSRC
SPEN
EEIE
Bit 7
EEIF
Bit 7
EEIF
EEIE
CMIF
CMIE
CMIF
CMIE
Bit 6
Bit 6
RX9
TX9
RX9
TX9
SREN CREN
TXEN SYNC
SREN CREN
TXEN SYNC
RCIF
RCIE
Bit 5
RCIF
RCIE
Bit 5
Bit 4
TXIF
TXIE
Bit 4
TXIF
TXIE
Preliminary
ADEN
ADEN
Bit 3
Bit 3
—
—
—
—
—
—
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000
2.
3.
4.
5.
6.
7.
8.
CCP1IE TMR2IE TMR1IE 0000 -000
CCP1IF TMR2IF TMR1IF 0000 -000
BRGH
FERR
BRGH
FERR
Bit 2
Bit 2
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
OERR
TRMT
OERR
TRMT
Bit 1
Bit 1
RX9D
TX9D
RX9D
TX9D
Bit 0
Bit 0
PIC16F62X
0000 -00x
0000 0000
0000 -010
0000 0000
0000 -00x
0000 0000
0000 -010
0000 0000
Value on
Value on
POR
POR
DS40300C-page 85
Value on all
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
Value on all
0000 -000
0000 -00x
0000 0000
0000 -000
0000 -010
0000 0000
RESETS
RESETS
other
other