PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 285

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 22-16: I
© 2006 Microchip Technology Inc.
100
101
102
103
90
91
106
107
92
109
110
D102
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
Param.
No.
2: A Fast mode I
T
T
T
T
T
T
T
T
T
T
T
C
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
T
released.
SU
SU
SU
AA
Symbol
HIGH
LOW
R
F
HD
HD
BUF
B
R
:
:
:
max. + T
:
:
STA
DAT
STO
STA
DAT
2
C BUS DATA REQUIREMENTS (SLAVE MODE)
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time 100 kHz mode
STOP condition
setup time
Output valid from
clock
Bus free time
Bus capacitive loading
SU
2
:
DAT
C bus device can be used in a Standard mode I
= 1000 + 250 = 1250 ns (according to the Standard mode I
Characteristic
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
2
CY
CY
C bus system, but the requirement T
B
B
1000
1000
3500
Max
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C bus specification) before the SCL line is
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
PIC18FXX2
PIC18FXXX must operate at a
minimum of 1.5 MHz
PIC18FXXX must operate at a
minimum of 10 MHz
PIC18FXXX must operate at a
minimum of 1.5 MHz
PIC18FXXX must operate at a
minimum of 10 MHz
C
10 to 400 pF
V
V
Only relevant for Repeated
START condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission can
start
B
DD
DD
is specified to be from
4.2V
4.2V
Conditions
DS39564C-page 283
SU
:
DAT
250 ns