PIC18F4620-I/PT Microchip Technology Inc., PIC18F4620-I/PT Datasheet - Page 81

• Manufacturer Part Number: PIC18F4620-I/PT
• Description: 44 Pin, 64 KB Flash, 3968 RAM, 36 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F4620-I/PT

• A/d Inputs: 13-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 36
• Interface: SPI/I2C/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 64K Bytes
• Ram Size: 4K Bytes
• Speed: 40 MHz
• Timers: 1-8 bit, 3-16 bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.5
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed
64 times for each programming operation. All of the
table write operations will essentially be short writes
because only the holding registers are written. At the end
of updating the 64 holding registers, the EECON1
register must be written to in order to start the
programming operation with a long write.
FIGURE 6-5:
6.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
 2004 Microchip Technology Inc.
TBLPTR = xxxxx0
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer register with address being
erased.
Execute the row erase procedure.
Load Table Pointer register with address of first
byte being written.
Write the 64 bytes into the holding registers with
auto-increment.
Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY
WRITE SEQUENCE
Holding Register
TABLE WRITES TO FLASH PROGRAM MEMORY
8
TBLPTR = xxxxx1
Holding Register
PIC18F2525/2620/4525/4620
8
Preliminary
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
8.
9.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note:
Note:
Holding Register
Disable interrupts.
Write 55h to EECON2.
2 ms using internal timer).
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 64 holding registers
before executing a write operation.
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
8
TBLPTR = xxxx3F
Holding Register
DS39626B-page 79
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