PIC16F690-E/P Microchip Technology Inc., PIC16F690-E/P Datasheet - Page 191

• Manufacturer Part Number: PIC16F690-E/P
• Description: 20 PIN, 7 KB FLASH, 256 RAM, 18 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F690-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 7 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 18
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

13.12.4
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RB6/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR
register. Then, pin RB6/SCK/SCL should be enabled
by setting bit CKP (SSPCON<4>). The master must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 13-10).
FIGURE 13-10:
© 2006 Microchip Technology Inc.
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
TRANSMISSION
A7
1
Data in
sampled
A6
2
I
2
C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
3
A4
4
A3
5
PIC16F631/677/685/687/689/690
A2
6
A1
7
R/W = 1
8
Preliminary
9
ACK
responds to SSPIF
while CPU
SCL held low
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another
occurrence of the Start bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR
register. Then pin RB6/SCK/SCL should be enabled by
setting bit CKP.
D7
1
SSPBUF is written in software
D6
2
Cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D5
3
D4
4
Transmitting Data
D3
5
D2
6
From SSP Interrupt
Service Routine
D1
7
DS41262C-page 189
D0
8
ACK
9
P