DS26521L+ Maxim Integrated Products, DS26521L+ Datasheet - Page 54

• Manufacturer Part Number: DS26521L+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521L+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 220 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-19. T1 Alarm Criteria
Note 1:
Note 2:
8.9.8 E1 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is
enabled (TCR2.6 = 1), the device monitors the receive-side framer to determine if any of the following conditions
are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or
signal). If any one (or more) of these conditions is present, the framer forces an AIS.
When automatic RAI generation is enabled (TCR2.5 = 1), the framer monitors the receive side to determine if any
of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, loss of
receive carrier (or signal), or if CRC-4 multiframe synchronization cannot be found within 128ms of FAS
synchronization (if CRC-4 is enabled). If any one (or more) of the above conditions is present, the framer transmits
an RAI alarm. RAI generation conforms to ETS 300 011 and ITU-T G.706 specifications.
Note: It is an illegal state to have both automatic AIS generation and automatic remote alarm generation enabled
at the same time.
8.9.8.1 Receive AIS-CI and RAI-CI Detection
AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all-ones pattern and 0.15
seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in
length in which, if the first bit is numbered bit 0, bits 3088, 3474, and 5790 are logical zeros and all other bits in the
pattern are logical ones (T1.403). AIS-CI is an unframed pattern, so it is defined for all T1 framing formats. The
RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1.2) is set. RAIS-CI is a latched bit
that should be cleared by the host when read. RAIS-CI continues to set approximately every 1.2 seconds that the
condition is present. The host needs to poll the bit in conjunction with the normal AIS indicators to determine when
the condition has cleared.
(Note: This alarm is also referred to
(Yellow
Alarm)
RAI
as receive carrier loss (RCL).)
(Blue Alarm) (See Note 1)
The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all-ones signal. AIS detectors should be able to operate
properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all-ones signal. The AIS alarm criteria
in the DS26521 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit.
The following terms are equivalent:
(Loss of Signal)
1) D4 Bit 2 Mode
(T1RCR2.0 = 0)
2) D4 12th F-Bit Mode
(T1RCR2.0 = 1)
(Note: This mode is
also referred to as the
“Japanese Yellow
Alarm.”)
3) ESF Mode
RAIS = Blue Alarm
RLOS = RCL
RLOF = Loss of Frame (conventionally RLOS for Dallas Semiconductor devices)
RRAI = Yellow Alarm
ALARM
LOS
AIS
When over a 3ms window, 4 or
fewer zeros are received.
When bit 2 of 256 consecutive
channels is set to zero for at least
254 occurrences.
When the 12th framing bit is set to
one for two consecutive
occurrences.
When 16 consecutive patterns of
00FF appear in the FDL.
When 192 consecutive zeros are
received.
SET CRITERIA
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DS26521 Single T1/E1/J1 Transceiver
When over a 3ms window, 5 or
more zeros are received.
When bit 2 of 256 consecutive
channels is set to zero for less than
254 occurrences.
When the 12th framing bit is set to
zero for two consecutive
occurrences.
When 14 or fewer patterns of 00FF
hex out of 16 possible appear in the
FDL.
When 14 or more ones out of 112
possible bit positions are received
starting with the first one received.
CLEAR CRITERIA