PIC16F676-I/ST Microchip Technology Inc., PIC16F676-I/ST Datasheet - Page 12

• Manufacturer Part Number: PIC16F676-I/ST
• Description: 14 PIN, 1.75 KB FLASH, 64 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F676-I/ST

• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin TSSO
• Programmable Memory: 1.75K Bytes
• Ram Size: 64 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
Addr
PIC16F630/676
TABLE 2-2:
DS40039C-page 10
2:
3:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCAL
ANSEL
WPUA
IOCA
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
IRP & RP1 bits are reserved, always maintain these bits clear.
PIC16F676 only.
Name
—
—
—
—
—
—
—
—
—
—
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
(3)
(3)
(3)
PIC16F630/676 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEPROM data register
EEPROM control register 2 (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
Bit 7
RAPU
IRP
ANS7
VREN
CAL5
EEIE
GIE
—
—
—
—
—
—
—
—
—
(2)
EEPROM address register
INTEDG
ADCS2
RP1
Bit 6
ANS6
ADIE
CAL4
PEIE
—
—
—
—
—
—
—
—
(2)
TRISA5
TRISC5
WPUA5
ADCS1
IOCA5
Bit 5
ANS5
T0CS
CAL3
T0IE
VRR
RP0
—
—
—
—
Write buffer for upper 5 bits of program counter
TRISC4
WPUA4
TRISA4
ADCS0
IOCA4
Bit 4
T0SE
CAL2
ANS4
INTE
TO
—
—
—
—
WRERR
TRISA3
TRISC3
IOCA3
Bit 3
ANS3
CMIE
CAL1
RAIE
PSA
VR3
PD
—
—
—
TRISA2
TRISC2
WPUA2
IOCA2
WREN
Bit 2
CAL0
ANS2
T0IF
VR2
PS2
—
—
—
Z
TRISA1
TRISC1
WPUA1
IOCA1
Bit 1
ANS1
INTF
POR
PS1
VR1
WR
DC
—
—
—
 2003 Microchip Technology Inc.
TMR1IE
TRISA0
TRISC0
WPUA0
IOCA0
Bit 0
ANS0
RAIF
BOD
VR0
PS0
RD
—
—
C
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
--11 1111
---0 0000
0000 0000
00-- 0--0
---- --qq
1000 00--
1111 1111
--11 -111
--00 0000
0-0- 0000
0000 0000
0000 0000
---- x000
---- ----
xxxx xxxx
-000 ----
Value on
POR,
BOD
—
—
—
—
—
—
—
—
—
—
Page
18,61
12,30
45,61
17
11
18
19
17
13
14
16
16
46
20
21
42
49
49
50
49
44
—
—
—
—
—
—
—
—
—
—