FM32256-G Ramtron, FM32256-G Datasheet - Page 4

• Manufacturer Part Number: FM32256-G
• Description: Supervisory Circuits 256K w/Pwr Mon WDT Bat Sw Pwr Fail
• Manufacturer: Ramtron

Specifications of FM32256-G

• Number Of Voltages Monitored: 4
• Monitored Voltage: 2.6 V, 2.9 V, 3.9 V, 4.4 V
• Output Type: Active Low, Bidirectional
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1500 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
The FM32xx family combines a serial nonvolatile
RAM with a processor companion. The companion is
a highly integrated peripheral including a processor
supervisor, a comparator used for early power-fail
warning, nonvolatile event counters, and a 64-bit
serial
complementary but distinct functions that share a
common interface in a single package. Although
monolithic, the product is organized as two logical
devices, the FRAM memory and the companion.
From the system perspective they appear to be two
separate devices with unique IDs on the serial bus.
The FM32xx provides the same functions as the
FM31xx with the exception of the real-time clock.
This makes it easy to develop a common design that
can either include timekeeping by using the FM31xx
or exclude it by using the FM32xx. All other features
are identical. The register address map is even
preserved so that software can be identical.
The memory is organized as a stand-alone 2-wire
nonvolatile memory with a standard device ID value.
The companion functions are accessed under their
own 2-wire device ID. This allows the companion
functions to be read while maintaining the most
recently used memory address. The companion
functions are controlled by 16 special function
registers. The event counter circuits and related
registers are maintained by the power source on the
VBAK pin, allowing them to operate from battery or
backup capacitor power when V
threshold. Each functional block is described below.
Memory Operation
The FM32xx is a family of products available in
different memory sizes including 4Kb, 16Kb, 64Kb,
and 256Kb. The family is software compatible, all
versions use consistent two-byte addressing for the
memory device. This makes the lowest density
device different from its stand-alone memory
counterparts but makes them compatible within the
entire family.
Memory is organized in bytes, for example the 4Kb
memory is 512 x 8 and the 256Kb memory is 32,768
x 8. The memory is based on FRAM technology.
Therefore it can be treated as RAM and is read or
written at the speed of the two-wire bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The 2-wire interface protocol
is described further on page 13.
The memory array can be write-protected by
software. Two bits in the processor companion area
Rev. 3.1
July 2010
number. The FM32xx integrates these
DD
drops below a set
(WP0, WP1 in register 0Bh) control the protection
setting as shown in the following table. Based on the
setting, the protected addresses cannot be written and
the 2-wire interface will not acknowledge any data to
protected addresses. The special function registers
containing these bits are described in detail below.
Processor Companion
In addition to nonvolatile RAM, the FM32xx family
incorporates
companion. It includes a low voltage reset, a
programmable watchdog timer, battery-backed event
counters, a comparator for early power-fail detection
or other purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic
functions: detection of power supply fault conditions
and a watchdog timer to escape a software lockup
condition. All FM32xx devices have a reset pin
(/RST) to drive the processor reset input during
power faults (and power-up) and software lockups. It
is an open drain output with a weak internal pull-up
to V
OR’d to the /RST pin. When V
programmed trip point, /RST output is pulled weakly
to V
voltage level (V
will remain low until V
operation which is the V
again above V
at least 100 ms (t
at a reliable V
/RST pin will return to the weak high state. While
/RST is asserted, serial bus activity is locked out even
if a transaction occurred as V
A memory operation started while V
will be completed internally.
Figure 2 below illustrates the reset operation in
response to the V
VDD
VTP
RST
DD
DD
Write protect addresses
None
Bottom 1/4
Bottom 1/2
Full array
. This allows other reset sources to be wire-
. If V
Figure 2. Low Voltage Reset
DD
TP
DD
a
TP
, /RST will continue to drive low for
DD
RPU
) the /RST pin will be driven low. It
level. After t
drops below the reset trip point
voltage.
highly
) to ensure a robust system reset
DD
RST
falls too low for circuit
level. When V
DD
integrated
RPU
dropped below V
FM3204/16/64/256
WP1
has been met, the
DD
0
0
1
1
DD
is above the
is above V
WP0
Page 4 of 21
processor
DD
0
1
0
1
t
RPU
rises
TP
TP
.