FM32256-G Ramtron, FM32256-G Datasheet - Page 6

• Manufacturer Part Number: FM32256-G
• Description: Supervisory Circuits 256K w/Pwr Mon WDT Bat Sw Pwr Fail
• Manufacturer: Ramtron

Specifications of FM32256-G

• Number Of Voltages Monitored: 4
• Monitored Voltage: 2.6 V, 2.9 V, 3.9 V, 4.4 V
• Output Type: Active Low, Bidirectional
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 1500 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-14
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The voltage on the PFI input pin is compared to an
onboard 1.2V reference. When the PFI input voltage
drops below this threshold, the comparator will drive
the PFO pin to a low state. The comparator has 100
mV (max) of hysteresis to reduce noise sensitivity,
only for a rising PFI signal. For a falling PFI edge,
there is no hysteresis.
The comparator is a general purpose device and its
application is not limited to the NMI function.
Note: The maximum voltage on the comparator input
PFI is limited to 3.75V under normal operating
conditions.
Event Counter
The FM32xx offers the user two battery-backed event
counters.
programmable edge detectors. Each clocks a 16-bit
counter. When an edge occurs, the counters will
increment their respective registers. Counter 1 is
located in registers 0Dh and 0Eh, Counter 2 is
located in registers 0Fh and 10h. These register
values can be read anytime V
they will be incremented as long as a valid VBAK
power source is provided. To read, set the RC bit
register 0Ch bit 3 to 1. This takes a snapshot of all
four counter bytes allowing a stable value even if a
count occurs during the read. The registers can be
written by software allowing the counters to be
cleared or initialized by the system. Counts are
blocked during a write operation. The two counters
can be cascaded to create a single 32-bit counter by
setting the CC control bit (register 0Ch). When
cascaded, the CNT1 input will cause the counter to
increment. CNT2 is not used in this mode.
The control bits for event counting are located in
register 0Ch. Counter 1 Polarity is bit C1P, bit 0;
Counter 2 Polarity is C2P, bit 1; the Cascade Control
is CC, bit 2; and the Read Counter bit is RC bit 3.
The polarity bits must be set prior to setting the
counter value(s). If a polarity bit is changed, the
Rev. 3.1
July 2010
CNT1
CNT2
C1P
C2P
Input
Figure 6. Event Counter
CC
pins
CNT1
DD
16-bit Counter
16-bit Counter
is above V
and
CNT2
TP
, and
are
counter may inadvertently increment. If the counter
pins are not being used, tie them to ground.
Serial Number
A memory location to write a 64-bit serial number is
provided. It is a writeable nonvolatile memory block
that can be locked by the user once the serial number
is set. The 8 bytes of data and the lock bit are all
accessed via the device ID for the processor
companion. Therefore the serial number area is
separate and distinct from the memory array. The
serial number registers can be written an unlimited
number of times, so these locations are general
purpose memory. However once the lock bit is set the
values cannot be altered and the lock cannot be
removed. Once locked the serial number registers can
still be read by the system.
The serial number is located in registers 11h to 18h.
The lock bit is SNL, register 0Bh bit 7. Setting the
SNL bit to a 1 disables writes to the serial number
registers, and the SNL bit cannot be cleared.
Backup Power
The event counter and battery-backed registers may
be powered with a backup power source. When the
primary system power fails, the voltage on the V
pin will drop. When V
counters and battery-backed registers will switch to
the backup power supply on V
Trickle Charger
To facilitate capacitor backup the V
optionally provide a trickle charge current. When the
VBC bit, register 0Bh bit 2, is set to 1 the V
will source approximately 15 µA until V
V
charges the capacitor to V
diode and resistor charger. In 5V systems, it provides
the same convenience and also prevents the user from
exceeding the V
In the case where no battery is used, the V
should be tied according to the following conditions:
DD
• For 3.3V systems, V
• For 5V systems, attach a 1 µF capacitor to V
or 3.75V whichever is less. In 3V systems, this
This assumes V
and turn the trickle charger on. The V
will charge to the internal backup voltage which
regulates itself to about 3.6V. V
be tied to 5V since the V
will be exceeded. A 1 µF capacitor will keep
the companion functions working for about 1.5
second.
BAK
maximum voltage specification.
DD
DD
does not exceed 3.75V.
is less than 2.5V, the event
BAK
DD
BAK
BAK
should be tied to V
without an external
.
FM3204/16/64/256
(max) specification
BAK
BAK
BAK
should not
Page 6 of 21
pin can
BAK
BAK
BAK
reaches
BAK
pin
pin
pin
DD
DD
.