TP3410J National Semiconductor, TP3410J Datasheet - Page 14

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Figure 7 shows the frame structure at the GCI interface
Functional Description
8 2 GCI Frame Structure
One GCI channel supports one TP3410 using a bandwidth
of 256 kbit s consisting of the following channels multi-
plexed together in an 8 kHz frame
8 3 Monitor Channel
The GCI Monitor channel (byte 3) is used to access all the
Command Registers shown in Table II with the exception of
the Activation Control Register and all the Status Registers
shown in Table III with the exception of the Activation Indi-
cation Register Each access to or from one of the listed
registers requires a 2-byte message transfer As shown in
Tables II and III the first byte from the originating device
contains the register address and the second byte is the
data byte Status Registers originate messages in the Moni-
tor channel under control of the Interrupt Stack (in the same
manner as when the TP3410 is used in Microwire Mode) In
addition a protocol is used based on the E and A bits in
byte 4 to provide an acknowledgement of each Monitor
channel byte in either direction see Figure 8
When no Monitor Channel message is being transferred
the E bit and the A bit in the reverse direction are high-im-
pedance (and pulled high by the external resistor if no other
Note 1 As an output (GCI Master) FS
Note 2 The FSb output is provided only in GCI Master Mode
B1 channel at 8 bits per frame
B2 channel at 8 bits per frame
Monitor (M) channel at 8 bits per frame
Signalling and Control (SC) channel which is structured
as follows
D Channel at 2 bits per frame
C I channel at 4 bits per frame
A bit for acknowledgement of M channel bytes
E bit which indicates byte boundaries when multiple-
byte messages are transferred via the M channel
FIGURE 7 GCI Frame Structure is an Example of Multiplex Mode with BCLK
a
is high for 8-bit intervals (16 BCLK cycles) As an input (GCI Slave) FS
FIGURE 8 GCI Monitor Channel and E and A Bit Protocol
(Continued)
14
device is active in that channel) To initiate a transfer a
device must first verify that it has received the A bit
least 2 consecutive GCI frames from the other device be-
fore starting the transfer It then sends the first byte in the
Monitor channel with the associated E bit
the byte in the next GCI frame Normally the receiving de-
vice will verify receiving the same byte in 2 consecutive
frames and acknowledge this by setting A
frames If not the message is aborted by sending A
only 1 frame
On detecting the acknowledgement the sending device
then sends the 2nd of the 2 bytes in 2 consecutive GCI
frames (or until it is acknowledged) with E
this is the last byte of the transfer The receiver verifies this
byte is the same for 2 frames and sends an acknowledge-
ment by sending A
quired the receiver will maintain A
Monitor channel message originated by the TP3410 is
aborted it will repeat the complete message until it is suc-
cessfully acknowledged
8 4 C I Channel
The C I (Command Indicate) channel in GCI byte 4 is used
solely to access the Activation Control Register and the Ac-
tivation Indication Register in the TP3410 A complete de-
scription of these registers is found in Section 11 including
the coding of the 4-bit messages Unlike the Microwire
Mode of the device however the contents of these 2 regis-
ters are transferred repeatedly in the C I channel once per
GCI frame A change in transmit message is originated by a
change in the Activation Indication Register while a change
in received message is verified in 2 consecutive GCI frames
before updating the Activation Control Register and taking
the appropriate action
e
a
1 in the next frame If an abort is re-
must be high for
e
4 096 MHz
e
t
1 for another frame If a
1 BCLK cycle
e
e
e
0 for at least 2
0 and repeats
1 to indicate
TL H 9151 – 16
TL H 9151 – 27
e
1 for at
e
0 for