TP3410J National Semiconductor, TP3410J Datasheet - Page 2

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Connection Diagrams
Pin Descriptions
No
Pin
24
23
21
20
10
9
5
8
Symbol
GNDA
GNDD1
GNDD2
V
V
MCLK
XTAL
XTAL2
TSr
SCLK
CC
CC
A
D
Pin Names for MICROWIRE Mode
Negative power supply pins which must
be connected together close to the de-
vice All digital signals are referenced to
these pins which are normally at the sys-
tem 0V (Ground) potential
Positive power supply input for the analog
sections which must be
must be directly connected to V
Positive power supply input for the digital
section which must be
must be directly connected to V
The 15 36 MHz Master Clock input which
requires either a parallel resonance crystal
to be tied between this pin and XTAL2 or
a CMOS logic level clock input from a sta-
ble source (a TTL Logic ‘‘1’’ level is not
suitable) This clock does not need to be
synchronized to the system clock (BCLK
and FS) see Section 5 1
The output of the crystal oscillator which
should be connected to one end of the
crystal if used otherwise this pin must be
left open-circuit Not recommended to
drive additional logic
This pin has 2 functions in LT mode it is
an open-drain n-channel TSr output which
goes low only during the time-slots as-
signed to the B1 and B2 channels at the
Br pin in order to enable the TRI-STATE
control of the backplane line-driver In NT
mode it is a full CMOS 15 36 MHz syn-
chronous clock output which is frequency-
locked to the received line signal (unlike
the XTAL pins it is not free-running)
Top View
Description
a
a
5V
5V
See NS Package Number J28A
g
TL H 9151– 2
g
CC
CC
Order Number TP3410J
5% and
5% and
D
A
2
No
Pin
22 TSFS
25 LSD RSFS This pin is an open-drain n-channel Line
1 Lo
4 Lo
Symbol
b
a
Pin Names for GCI Mode
The Transmit Superframe Sync pin which
indicates the start of each 12 ms transmit
superframe at the U Interface In NT mode
this pin is always an output In LT mode it
may be selected to be either an input or
CMOS output via Register CR2 when se-
lected as an output the signal is a square-
wave Must be tied low if selected as input
yet not driven
Signal Detector output which is normally
high-impedance and pulls low only when
the device is powered down and an incom-
ing wake-up signal is detected from the
far-end As an option this pin can be pro-
grammed to be an output indicating the
start of the received superframe at the U
interface an external pull-up resistor is re-
quired
The RSFS signal indicates the start of
each 12 ms receive superframe from the U
Interface and is available in NT and LT
modes The Received Superframe Synch
clock output is accessible on pin 25 by
writing X’1C04 and X’100C (or X’100E)
during device initialization See TP3410
users manual AN-913 Part II Section
4 18)
Transmit 2B1Q signal differential outputs
to the line transformer When used with an
appropriate 1 1 5 step-up transformer and
the line coupling circuit recommended in
the Applications section the line signal
conforms to the output specifications in
the ANSI standard
Top View
Description
TL H 9151 – 3