DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 37

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 3-10:
TABLE 3-11:
TABLE 3-12:
TABLE 3-13:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
SFR Name
U1MODE
U1STA
U1TXREG
U1RXREG
U1BRG
Legend:
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
QEICON
DFLTCON
POSCNT
MAXCNT
Legend:
SFR Name
Name
Name
SFR
SFR
u = uninitialized bit, — = unimplemented, read as ‘0’
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
SFR
0240
0242
0244
0248
Addr.
SFR
0220
0222
0224
0226
0228
01E0 CNTERR
01E2
01E4
01E6
Addr
020A
020C
SFR
0200
0202
0204
0206
0208
QEI REGISTER MAP
I2C1 REGISTER MAP
UART1 REGISTER MAP
SPI1 REGISTER MAP
UTXISEL1
FRMEN
ACKSTAT
SPIEN
UARTEN
Bit 15
Bit 15
Bit 15
I2CEN
Bit 15
—
—
—
—
—
—
—
—
—
Bit 14
SPIFSD
UTXINV UTXISEL0
TRSTAT
Bit 14
—
—
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
QEISIDL
Bit 13
—
I2CSIDL
FRMPOL
SPISIDL
USIDL
Bit 13
Bit 13
Bit 13
—
—
—
—
—
—
—
—
—
Bit 12 Bit 11 Bit 10
INDX
—
SCLREL
DISSCK
Bit 12
Bit 12
Bit 12
IREN
—
—
—
—
—
—
—
—
—
—
—
UPDN
—
UTXBRK
RTSMD
DISSDO
IPMIEN
Bit 11
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
—
IMV<1:0>
QEIM<2:0>
Bit 9
UTXEN
MODE16
Bit 10
Bit 10
Bit 10
A10M
—
—
—
BCL
—
—
—
—
—
—
—
CEID
Bit 8
Maximum Count<15:0>
Position Counter<15:0>
SPI1 Transmit and Receive Buffer Register
UTXBF
UEN1
GCSTAT
Bit 9
DISSLW
Bit 9
—
—
SMP
Bit 9
—
—
SWPAB PCDOUT
QEOUT
—
—
—
Baud Rate Generator Prescaler
Bit 7
UEN0
TRMT
Bit 8
ADD10
Bit 8
SMEN
CKE
Bit 8
—
—
—
—
Bit 6
WAKE
Bit 7
SSEN
IWCOL
URXISEL<1:0>
Bit 7
QECK<2:0>
GCEN
Bit 7
—
—
TQGATE
Bit 5
LPBACK
SPIROV
Bit 6
STREN
I2COV
Bit 6
CKP
Bit 6
—
Bit 4
TQCKPS<1:0>
Address Mask Register
MSTEN
ABAUD
ADDEN
ACKDT
Bit 5
Baud Rate Generator Register
Bit 5
Address Register
Bit 5
D_A
UART Transmit Register
—
—
UART Receive Register
Bit 3
—
URXINV
RIDLE
ACKEN
Bit 4
Bit 4
Transmit Register
Bit 4
Receive Register
—
—
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
P
Bit 2
—
SPRE<2:0>
BRGH
PERR
Bit 3
RCEN
Bit 3
Bit 3
—
—
S
Bit 1
—
FERR
Bit 2
Bit 2
Bit 2
R_W
PEN
—
—
PDSEL<1:0>
Bit 0
—
FRMDLY
SPITBF
OERR
Bit 1
Bit 1
RSEN
Bit 1
RBF
PPRE<1:0>
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
URXDA
Reset State
STSEL
SPIRBF
Bit 0
Bit 0
Bit 0
SEN
TBF
—
Resets
Resets
Resets
0000
0110
xxxx
0000
0000
0000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All
All