DSPIC33FJ32MC204-I/PT Microchip Technology Inc., DSPIC33FJ32MC204-I/PT Datasheet - Page 59

• Manufacturer Part Number: DSPIC33FJ32MC204-I/PT
• Description: 16-BIT DSC, 44LD, 32KB FLASH, MOTOR, 40 MIPS, NANOWATT
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC33FJ32MC204-I/PT

• A/d Inputs: 9-Channels, 10-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 35
• Interface: I2C, SPI, UART/USART
• Ios: 35
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 44-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Timers: 3-16-bit, 1-32-bit
• Voltage, Range: 3-3.6 V
• Dc: 08+
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

5.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode, Uninitialized W Regis-
• CM: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
shown in Figure 5-1.
FIGURE 5-1:
© 2007 Microchip Technology Inc.
Note:
ter Reset and Security Reset
RESETS
This data sheet summarizes the features
of
dsPIC33FJ16MC304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “dsPIC33F
Family Reference Manual”. Please see
the Microchip web site (www.micro-
chip.com) for the latest dsPIC33F Family
Reference Manual sections.
the
MCLR
V
DD
Uninitialized W Register
Configuration Mismatch
dsPIC33FJ32MC202/204
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
Illegal Opcode
Module
WDT
Trap Conflict
V
Detect
DD
Glitch Filter
Rise
and
Preliminary
BOR
POR
Any active source of Reset makes the SYSRST signal
active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 5-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user appli-
cation can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
SYSRST
DS70283B-page 57