GS84036AT-150I GSI TECHNOLOGY, GS84036AT-150I Datasheet - Page 13

GS84036AT-150I

Manufacturer Part Number
GS84036AT-150I
Description
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS84036AT-150I

Density
4Mb
Access Time (max)
10ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
83.3MHz
Operating Supply Voltage (typ)
3.3V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
-40C to 85C
Number Of Ports
4
Supply Current
175mA
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Word Size
36b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Synchronous Truth Table
Rev: 1.19 10/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
7.
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
X = Don’t Care, H = High, L = Low.
E = T (True) if E
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Operation
2
= 1 and E
3
= 0; E = F (False) if E
Address
External
External
External
Current
Current
Current
Current
Used
None
None
None
Next
Next
Next
Next
Diagram
2
= 0 or E
State
Key
CW
CW
CR
CR
W
X
X
X
R
R
13/31
5
3
= 1.
E
H
L
L
L
X
H
X
H
X
H
X
H
L
L
1
E
X
F
F
T
T
T
X
X
X
X
X
X
X
X
2
GS84018/32/36AT/B-180/166/150/100
ADSP ADSC
X
H
H
H
H
X
H
X
H
X
H
X
L
L
L
X
L
X
L
L
H
H
H
H
H
H
H
H
ADV
H
H
H
H
X
X
X
X
X
X
L
L
L
L
© 1999, GSI Technology
W
X
X
X
X
F
T
F
F
T
T
F
F
T
T
3
High-Z
High-Z
High-Z
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
4

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