MC100EP445FA ON Semiconductor, MC100EP445FA Datasheet - Page 15

• Manufacturer Part Number: MC100EP445FA
• Manufacturer: ON Semiconductor

Specifications of MC100EP445FA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LQFP
• Pin Count: 32
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

clock cycle pulse length will disable the internal clock
signal. The synchronous CKEN will suspend all of the
device activities and prevent runt pulses from being
generated. The rising edge of CKEN followed by the falling
framer and can help the user to synchronize the parallel data
outputs. During CKSEL LOW operation, the PCLK will
provide a divide by 4−clock frequency, which frames the
serial data in period of PCLK output. Likewise during
CKSEL HIGH operation, the PCLK will provide a divide by
8−clock frequency.
available to this device only. For single–ended input
The synchronous CKEN (pin 3) applied with at least one
The differential PCLK output (pins 22 and 23) is a word
The V
CKSEL
CKEN
PCLK
BB
CLK
pin, an internally generated voltage supply, is
Internal Clock
Disabled
Figure 12. Timing Diagram with CKEN with CKSEL HIGH
http://onsemi.com
Internal Clock
Enabled
15
edge of CLK will suspend all activities. The first data bit will
clock on the rising edge, since the falling edge of CKEN
followed by the falling edge of the incoming clock triggers
the enabling of the internal process. (See Figure 12)
conditions, the unused differential input is connected to V
as a switching reference voltage. V
coupled inputs. When used, decouple V
0.01 mF capacitor, which will limit the current sourcing or
sinking to 0.5mA. When not used, V
Also, both outputs of the differential pair must be terminated
(50 W to V
TT
= V
CC
– 2 V) even if only one output is used.
BB
BB
may also rebias AC
should be left open.
BB
and V
CC
via a
BB