ADV7305AKST Analog Devices Inc, ADV7305AKST Datasheet - Page 13

• Manufacturer Part Number: ADV7305AKST
• Description: IC ENCODER VIDEO 14BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7305AKST

• Applications: DVD, SD/HD
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 14b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No.
14–18, 26–30
19
20
21
22
23
24
25
31
32
33
34
35, 47
36, 45
37
38
39
40
41
42
43
44
46
48
49
50
51–55, 58–62
63
64
REV. A
Mnemonic
C0–C9
I
ALSB
SDA
SCLK
P_HSYNC
P_VSYNC
P_BLANK
RTC_SCR_TR
CLKIN_A
RESET
EXT_LF
R
COMP2, 1
DAC F
DAC E
DAC D
AGND
V
DAC C
DAC B
DAC A
V
S_BLANK
S_VSYNC
S_HSYNC
S0–S9
CLKIN_B
GND_IO
2
SET1, 2
AA
REF
C
I
I
I/O
I/O
I
I
I
I
I
I
I
I
I
O
O
G
P
O
O
O
I/O
I/O
I/O
I/O
I
I
Input/Output
O
O
Function
10-Bit Progressive Scan/HDTV Input Port for CrCb Color Data in 4:2:2
Input Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U)
data. The LSBs are set up on Pins C0 and C1. In Default Mode, the input on
this port is output on DAC E.
This input pin must be tied high (V
interface over the I
TTL Address Input. This signal sets up the LSB of the MPU address. When
this pin is tied low, the I
interface.
MPU Port Serial Data Input/Output
MPU Port Serial Interface Clock Input
Video Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
Video Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode
and HD Only Mode
Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,
and Subcarrier Reset Input
Pixel Clock Input for HD Only or SD Only Modes
This input resets the on-chip timing generator and sets the ADV7304A/
ADV7305A into default register setting. Reset is an active low signal.
External Loop Filter for the Internal PLL
A 1520 Ω resistor must be connected from this pin to AGND and is used to
control the amplitudes of the DAC outputs.
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V
In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pb/Blue (HD) Analog Output
In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pr/Red (HD) Analog Output
In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and
Simultaneous HD/SD: Y/Green (HD) Analog Output
Analog Ground
Analog Power Supply
Chroma/Red/V SD Analog Output
Luma/Blue/U SD Analog Output
CVBS/Green/Y SD Analog Output
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V)
Video Blanking Control Signal for SD
Video Vertical Control Signal for SD. Option to output SD VSYNC or SD
HSYNC in SD Slave Mode 0 and/or any HD Mode.
Video Horizontal Control Signal for SD. Option to output SD HSYNC or
HD HSYNC in SD Slave Mode 0 and/or any HD Mode.
10-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port
for Cr (Red/V) Color Data in 4:4:4 Input Mode. The LSBs are set up on Pins
S0 and S1. In Default Mode, the input on this port is output on DAC F.
Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This
clock input pin is only used in Simultaneous SD/HD Mode.
Digital Ground
–13–
2
C port.
2
C filter is activated, which reduces noise on the I
DD_IO
ADV7304A/ADV7305A
) for the ADV7304A/ADV7305A to
2
AA
C
.