SAF7129AH/V1,557 NXP Semiconductors, SAF7129AH/V1,557 Datasheet - Page 22

• Manufacturer Part Number: SAF7129AH/V1,557
• Description: IC DIGITAL VIDEO ENCODER 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Encoderr

Specifications of SAF7129AH/V1,557

• Package / Case: 44-QFP
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935274073557; SAF7129AH/V1; SAF7129AH/V1

Philips Semiconductors
Table 22 Subaddress 51H
Table 23 Subaddress 52H
Table 24 Subaddress 53H
Table 25 Subaddress 54H
2004 Mar 16
Digital video encoder
7 to 0
7 to 0
7 to 0
BIT
BIT
BIT
BIT
7
6
5
4
3
2
1
0
LUTU[7:0]
LUTV[7:0]
LUTY[7:0]
SYMBOL
SYMBOL
SYMBOL
SYMBOL
VPSEN
EDGE2
EDGE1
VPSEL
ENCIN
RGBIN
DELIN
LUT for the colour values inserted in case of key colour 2 U detection in the MPEG input
data stream.
LUTU[7:0] = 80H; default value after reset
LUT for the colour values inserted in case of key colour 2 V detection in the MPEG input
data stream.
LUTV[7:0] = 80H; default value after reset
LUT for the colour values inserted in case of key colour 2 Y detection in the MPEG input
data stream.
LUTY[7:0] = 80H; default value after reset
0 = video programming system data insertion is disabled; default state after reset
1 = video programming system data insertion in line 16 is enabled
This bit is not used and should be set to logic 0.
0 = encoder path is fed with MP
1 = encoder path is fed with output signal of fader; see Section 7.1
0 = RGB path is fed with MP
1 = RGB path is fed with output signal of fader; see Section 7.1
0 = not supported in current version; do not use
1 = recommended value; default state after reset
0 = not supported in current version; do not use
1 = recommended value; default state after reset
0 = MP
1 = MP
0 = MP
1 = MP
B
B
A
A
data is sampled on the rising clock edge; default state after reset
data is sampled on the falling clock edge
data is sampled on the rising clock edge; default state after reset
data is sampled on the falling clock edge
22
B
input data; fader is bypassed; default state after reset
B
input data; fader is bypassed; default state after reset
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAF7129AH
Product specification