SAF7129AH/V1,557 NXP Semiconductors, SAF7129AH/V1,557 Datasheet - Page 31

• Manufacturer Part Number: SAF7129AH/V1,557
• Description: IC DIGITAL VIDEO ENCODER 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Video Encoderr

Specifications of SAF7129AH/V1,557

• Package / Case: 44-QFP
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 935274073557; SAF7129AH/V1; SAF7129AH/V1

Philips Semiconductors
Table 52 Subaddress 6CH
Table 53 Subaddress 6DH
Table 54 Subaddress 6EH
Table 55 Selection of phase reset mode
2004 Mar 16
Digital video encoder
PHRES1
7 to 0
BIT
BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
0
1
1
HTRIG[7:0]
SYMBOL
SYMBOL
SYMBOL
HTRIG10
BLCKON
PHRES1
PHRES0
PHRES0
HTRIG9
HTRIG8
VTRIG4
VTRIG3
VTRIG2
VTRIG1
VTRIG0
SBLBN
LDEL1
LDEL0
FLC1
FLC0
0
1
0
1
These are the 8 LSBs of the 11-bit code that sets the horizontal trigger phase related to
the signal on RCV1 or RCV2 input. The 3 MSBs are held in subaddress 6DH;
see Table 53. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.
Increasing HTRIG[10:0] decreases delays of all internally generated timing signals.
Reference mark: analog output horizontal sync (leading slope) coincides with active
edge of RCV used for triggering at HTRIG[10:0] = 4FH (79).
These are the 3 MSBs of the horizontal trigger phase code; see Table 52.
Sets the vertical trigger phase related to signal on RCV1 input. Increasing VTRIG
decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG[4:0] = 0 to 31 (1FH).
0 = vertical blanking is defined by programming of FAL and LAL; default state after reset
1 = vertical blanking is forced in accordance with “ITU-R BT.624” (50 Hz) or RS170A
(60 Hz)
0 = encoder in normal operation mode
1 = output signal is forced to blanking level; default state after reset
These 2 bits select the phase reset mode of the colour subcarrier generator;
see Table 55.
These 2 bits select the delay on luminance path with reference to chrominance path;
see Table 56.
These 2 bits select field length control; see Table 57.
no reset or reset via RTCI from SAF7113 or SAF7118 if bit RTCE = 1; default value after
reset
reset every two lines or SECAM specific if bit SECAM = 1
reset every eight fields
reset every four fields
31
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAF7129AH
Product specification