PCA8575DK,118 NXP Semiconductors, PCA8575DK,118 Datasheet - Page 17

• Manufacturer Part Number: PCA8575DK,118
• Description: IC I/O EXPANDER I2C 16B 24QSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA8575DK,118

• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283504118; PCA8575DK-T; PCA8575DK-T

NXP Semiconductors
13. Dynamic characteristics
Table 6.
V
[1]
[2]
[3]
[4]
[5]
[6]
PCA8575_2
Product data sheet
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing; C
t
t
t
Interrupt timing; C
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
v(D)
d(rst)
DD
= 2.3 V to 5.5 V; V
t
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be suppressed
by the input filter
data output valid time
data input set-up time
data input hold time
data input valid time
reset delay time
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
L
f
100 pF (see
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
L
SS
100 pF (see
= 0 V; T
Figure 11
amb
f
.
Figure 11
= 40 C to +85 C; unless otherwise specified.
and
Figure
and
Rev. 02 — 21 March 2007
Figure
12)
Conditions
12)
Remote 16-bit I/O expander for I
[3][4]
[1]
[2]
[6]
0
1.3
0.6
0.6
0.6
0
0.1
50
100
1.3
0.6
20 + 0.1C
20 + 0.1C
-
-
0
4
-
-
Min
Fast mode I
b
b
[5]
[5]
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IL
of the SCL signal) in order to
2
C-bus with interrupt
2
C-bus
PCA8575
© NXP B.V. 2007. All rights reserved.
400
-
-
-
-
-
0.9
-
-
-
-
300
300
50
4
-
-
4
4
Max
f
is specified at
17 of 30
Unit
kHz
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s