AD9949KCPZ Analog Devices Inc, AD9949KCPZ Datasheet - Page 12

• Manufacturer Part Number: AD9949KCPZ
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9949KCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 40
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9949
SERIAL INTERFACE TIMING
The AD9949’s internal registers are accessed through a 3-wire
serial interface. Each register consists of an 8-bit address and a
24-bit data-word. Both the 8-bit address and 24-bit data-word
are written starting with the LSB. To write to each register, a
32-bit operation is required, as shown in Figure 14. Although
many registers are less than 24 bits wide, all 24 bits must be
written for each register. If the register is only 16 bits wide, then
the upper eight bits may be filled with zeros during the serial
write operation. If fewer than 24 bits are written, the register
will not be updated with new data.
SDATA
SCK
SL
SDATA
SCK
HD
VD
SL
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
NOTES
1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
A0
1
A0
A1
1
2
t
A1
LS
A2
2
3
A2
8-BIT ADDRESS
A3
3
4
A3
t
DS
A4
4
5
A4
A5
5
6
A5
A6
6
7
A6
Figure 15. Continuous Serial Write Operation
t
A7
7
DH
8
A7
Figure 14. Serial Write Operation
D0
8
9
D0
DATA FOR STARTING
REGISTER ADDRESS
D1
Rev. B | Page 12 of 36
9
10
D1
10
...
...
...
D2
11
D3
D22 D23
Figure 15 shows a more efficient way to write to the registers by
using the AD9949’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word is
written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Address auto-increment may be used start-
ing with any register location and may be used to write to as few
as two registers or as many as the entire register space.
12
24-BIT DATA
31
...
...
...
...
...
32
D0
33
D21 D22
SL UPDATED
REGISTER ADDRESS
30
D1
34
DATA FOR NEXT
31
...
...
...
D23
32
D22 D23
t
LH
55
56
VD/HD UPDATED
D0
57
D1
58
D2
59
...
...
...