X96012V14IZ Intersil, X96012V14IZ Datasheet
X96012V14IZ
Specifications of X96012V14IZ
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X96012V14IZ Summary of contents
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... NUMBER MARKING RANGE (°C) X96012V14I X9601 2VI -40 to +100 14 Ld TSSOP M14.173 X96012V14IZ* X9601 2VIZ -40 to +100 14 Ld TSSOP (Note) *Add “-T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets ...
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Block Diagram REFERENCE VREF VSENSE TEMPERATURE SENSOR SDA SCL WP A2, A1, A0 Pin Descriptions PIN PIN NUMBER NAME 1 A0 Device Address Select Pin 0. This pin determines the LSB of the device address required to communicate using the ...
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... X96012 Thermal Information Thermal Resistance (Typical, Note 1) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C Temperature While Writing to Memory . . . . . . . . . . . . 0°C to +70°C Voltage on V Voltage on any other Pin . . . . . . . . . . . . . . . . . . . . . . . . . V . All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between ...
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Electrical Specifications Conditions are as follows, unless otherwise specified. All typical values are for T Maximum and minimum specifications are over the recommended operating conditions. All voltages are referred to the voltage at pin V R and V 1 external ...
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D/A Converter Characteristics SYMBOL PARAMETER Overshoot on D/A Converter Data Byte OVER Transition Undershoot on D/A Converter Data Byte UNDER Transition Rise Time on D/A Converter Data Byte ...
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A/D Converter Characteristics SYMBOL PARAMETER NOTES: 14. LSB” is defined as V(VRef)/255, “Full-Scale” is defined as V(VRef). 15. Offset : For an ideal converter, the first transition of its transfer curve occurs at ADC deviation between the measured first transition ...
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Nonvolatile WRITE Cycle Timing SYMBOL PARAMETER t (Note 17) Nonvolatile Write Cycle Time WC NOTES: 16 total capacitance of one bus line (SDA or SCL) in pF. 17 the time from a valid STOP condition at ...
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... The general purpose memory portion of the device is a CMOS serial EEPROM array with Intersil’s Block Lock protection. The EEPROM array is internally organized as 272x8 bits with 16-Byte pages, and utilizes Intersil’s proprietary Direct Write Page Write cycles and a minimum data retention of 100 ° ...
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Principles of Operation Control and Status Registers The Control and Status Registers provide the user with a mechanism for changing and reading the value of various parameters of the X96012. The X96012 contains seven Control, one Status, and several Reserved ...
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L1DA5 - L1DA0: LUT1 DIRECT ACCESS BITS When bit L1DAS (bit 4 in Control register 5) is set to “1”, LUT1 is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. ...
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BYTE MSB ADDRESS 6 7 80h I2DS I1DS NON-VOLATILE I1 AND I2 DIRECTION CONTROL 0: SOURCE SINK VOLATILITY 0: VOLATILE 1: NON- DIRECT ACCESS TO LUT1 81h VOLATILE OR RESERVED RESERVED NON-VOLATILE DIRECT ACCESS TO ...
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Control Register 4 This register is accessed by performing a Read or Write operation to address 84h of memory. This byte’s volatility is determined by bit NV1234 in Control register 0. D2DA7 - D2DA0: D/A 2 DIRECT ACCESS BITS When ...
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Voltage Reference The voltage reference to the A/D and D/A converters on the X96012, may be driven from the on-chip voltage reference, or from an external source via the VREF pin. Bit VRM in Control Register 0 selects between the ...
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Look-Up Tables The X96012 memory array contains two 64-byte look-up tables. One is associated to pin I1’s output current generator and the other to pin I2’s output current generator, through their corresponding D/A converters. The output of each look-up table ...
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LUT2 ROW SELECTION BITS D0H LUT1 ROW SELECTION BITS 90H By examining the block diagram in Figure 8, we see that the maximum current through pin I1 is set by fixing values for V(VREF) and R . The output current ...
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VOLTAGE V ADCOK 0V CURRENT I X 10% X FIGURE 11. D/A CONVERTER POWER-ON RESET RESPONSE VOLTAGE REFERENCE VOLTAGE INPUT The A/D converter is shared between the two current generators but the look-up tables, D/A converters, control bits, and selection ...
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During all the previous sequence the input of both DACs are 00h. If bit ADCfiltOff is “1”, only one ADC conversion is necessary. Bits D1DAS, D2DAS, L1DAS, and L2DAS, also modify the way the two DACs are accessed the first ...
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SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER X96012 Memory Map The X96012 contains a 2176 bit array of mixed volatile and nonvolatile memory. This array is split up into ...
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Slave Address Byte Following a START condition, the master must output a Slave Address Byte. Refer to Figure 16. This byte includes three parts: • The four MSBs (SA7 - SA4) are the Device Type Identifier, which must always be ...
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SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE SLAVE S SIGNALS FROM T THE MASTER SIGNAL AT SDA 1 0 SIGNALS FROM THE SLAVE 7 BYTES ADDRESS = 0 FIGURE 20. EXAMPLE: WRITING 12 BYTES ...
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The four registers Control 1 through 4, have a nonvolatile and a volatile cell for each bit. At power-up, the content of the nonvolatile cells is automatically recalled and written to the volatile cells. The content of the volatile cells ...
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Data Protection There are four levels of data protection designed into the X96012: 1- Any Write to the device first requires setting of the WEL bit in Control 6 register; 2- The Block Lock can prevent Writes to certain regions ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...