AD9805JS Analog Devices Inc, AD9805JS Datasheet - Page 18

• Manufacturer Part Number: AD9805JS
• Description: IC CCD SIGNAL PROC 10BIT 64-PQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9805JS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: Microprocessor
• Current - Supply: 86mA
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

AD9807/AD9805
discharging include the amount of time that input switch S1 is
turned on, the input impedance of the AD9807/AD9805 and
the output impedance of the circuit driving the coupling
capacitor. The impedance of the drive circuit, R
impedance of the AD9807/AD9805, R
charging time, t
may not necessarily occur over a continuous period of time; it may
actually be an accumulation of discrete charging periods. This
is typical where CDSCLK1 is asserted only during the reset
levels of the pixels. In this case, the quantity, m T, may be
substituted for t
CDSCLK1 is asserted and T is the period of the assertion.
Given these quantities, the maximum value for the input
coupling capacitor is computed from the equation:
where V
capacitor and V
calculated by taking the difference between the CCD’s reset
level and the internal bias level of the AD9807/AD9805. V
the level of accuracy to which the input capacitor must be charged
and is system dependent. Usually the allowable droop of the
capacitor voltage is taken into account. This is discussed below.
For example, if the CCD output can droop up to 1 volt without
affecting the accuracy of the CDS, then clamping to within
about one tenth of the allowable droop (100 mV) should be
sufficient in most cases.
Calculating C
Determining C
voltage droop. It is important that the signals at the inputs of
the AD9807/AD9805 remain within the supply voltage limits so
the CDSs are able to accurately digitize the difference between
the reset level and the video level. Assuming the input voltages
are initially biased at the correct levels, the input bias current of
the AD9807/AD9805 inputs will discharge the input coupling
capacitors resulting in voltage droop. After taking into account
any droop, the peaks of the input signal must remain within the
required voltage limits of AD9807/AD9805 inputs.
Specifically, C
droop, dV, in one scan line, the number of pixels across one scan
line, n, the period of one pixel, t, and the input bias current of
the AD9807/AD9805, I
Some examples are given below showing the typical range of
capacitor values.
Example 1
A 5000 pixel CCD running at a 2 MHz (t = 500 ns) has a reset
level of 4.5 volts and an output voltage of 1.8 volts. The number
of optical black pixels available at the start of a line is 18. Using
the AD9807/AD9805 with an input span of 4 volts and a PGA
gain of 2 gives a V
to 3 volts during the optical black pixels, the required voltage
change on the input capacitor, V
and the maximum droop allowable during one line, dV, will be
(3 – 1.8) or 1.2 volts before the signal droops below 0 volts.
C
is the required voltage change across the coupling
MIN
MIN
MIN
ACQ
E
ACQ
is the maximum tolerable error voltage. V
C
BIAS
is a function of the amount of allowable
, are all known quantities. Note that t
is a function of the maximum allowable
MAX
, where m is the number of periods
C
of 3 volts. If the input signal is clamped
BIAS
MIN
R
. C
IN
MIN
t
ACQ
I
BIAS
dV
R
C
is calculated from the equation:
OUT
, equals (4.5 – 3) or 1.5 volts
/ ln
n t
IN
, and the desired
V
V
C
E
OUT
, the input
ACQ
C
E
is
is
–18–
Again, a larger capacitor may be used if several lines are allowed
for to initially charge up the cap, or if the CCD and CDSCLK1
are clocked during the moving of the scanner carriage.
With dV = 1.2 volts, a clamp accuracy of 100 mV should be
sufficient (V
amount of time available to charge up the input capacitor,
T
switch is closed) times the number of optical black pixels. With
a pixel rate of 2 MHz, CDSCLK1 would typically be around
100 ns wide, giving T
1.8 s. The input impedance of the AD9807 is 5K, and the
input bias current is 10 nA. Assume the source impedance
driving the AD9807 is low (R
Note that a capacitor larger than 133 pF would still work, it
would just take several lines to charge the input capacitor up
to the full V
clocking the CCD and CDSCLK1 while the transport motor
moves the scanner carriage. This would extend T
several hundred s or more, meaning that only very fine
adjustment would be needed during the limited number of
optical black pixels.
Example 2
A 7926 pixel CCD running at 2 MHz has a reset level of 6 volts,
an output voltage of 2.9 volts and 80 optical black pixels. Using
the AD9807 with an input span of 4 volts and a PGA gain of
1.25, V
on the capacitor, V
droop dV for one line is 1.1 volts. T
R
Generating 3-Channel Timing from a 16
Generating the required signals for CDSCLK1, CDSCLK2 and
ADCCLK is easily accomplished with a master clock running
16
requires 32 MHz master clock). The timing diagram shown
in Figure 18 meets all the minimum and maximum timing
specifications. Note that a 16
edges was chosen instead of using both edges of an 8 rate
clock to ensure immunity to duty cycle variations.
s, and V
OUT
ACQ
ADCCLK
CDSCLK1
CDSCLK2
MASTER
(32MHz)
Figure 18. Timing Scheme Using 16
the desired per channel pixel rate (i.e., 2 MSPS pixel rate
, will equal the period of CDSCLK1 (when the clamp
= 0, and I
BIAS
C
C
MIN
E
C
C
MAX
= 100 mV should be sufficient. Again, R
MIN
= 4 volts. The maximum required voltage change
MAX
1
E
C
= (10 nA/1.1)
=100 mV), but this value can be adjusted. The
level. Another option to lengthen T
= (1.8 s/5K)
2
= (10 nA/1.2)
BIAS
= (8 s/5K)
3
C
, is 2 volts and the maximum amount of
= 10 nA.
ACQ
4
5
=1800 ns or
6
OUT
(7926)
(1/ln (1.5/0.1)) = 133 pF
(1/ln (2/0.1))
7
5000
master clock using only rising
= 0).
500ns
8
ACQ
9
500 ns = 21 pF
(500 ns) = 36 pF
10
will be 80
11
Master Clock
Master Clock
12
534 pF
13
IN
ACQ
ACQ
100 ns or 8
14
= 5K,
is by
to
15
REV. 0
16