AD9895KBCRL Analog Devices Inc, AD9895KBCRL Datasheet - Page 29

• Manufacturer Part Number: AD9895KBCRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Example of Exposure and Readout of Interlaced Frame
Figure 35 shows the sequence of events for a typical exposure and
readout operation using a mechanical shutter and strobe. The
register values for the VSUB, MSHUT, and STROBE toggle
positions may be previously loaded at any time, prior to triggering
these functions. Additional register writes are required to configure
the vertical clock outputs, V1–V4, which are not described here.
0: Write to the READOUT Register (Addr x281) to specify
1: Write to the EXPOSURE Register (Addr x27D) to start the
REV. A
MECHANICAL
2: VD/HD falling edge will update the serial writes from 1.
3: If VSUB Mode = 0, VSUB output turns ON at the line
the number of fields to further suppress SUBCK while the
CCD data is readout. In this example, READOUT = 2.
exposure and specify the number of fields to suppress
SUBCK and VSG outputs during exposure. In this example,
EXPOSURE = 2.
Write to the TRIGGER Register (Addr x280) to enable the
STROBE, MSHUT, and VSUB signals. To trigger all three
signals (as in Figure 36) the register TRIGGER = 7.
Write to the SGACTLINE Register (Addr x265 and
Addr x266) and SGMASK Register (Addr x26F and
Addr x270) to configure the sensor gates for ODD field
readout (interlaced CCD).
specified in the VSUBON Register (Addr x272 and
Addr x273).
SHUTTER
STROBE
WRITES
SERIAL
SUBCK
MSHUT
VSUB
VSG
VD
Figure 35. Exposure and Readout of Interlaced Frame
MODE 0
t
EXP
–29–
10: VSG outputs returns to Draft/Preview Mode timing.
4: STROBE output turns OFF at the location specified in the
5: MSHUT Output turns OFF at the location specified in the
6: Write to the SGACTLINE Register (Addr x253 and
7: VD/HD falling edge will update the serial writes from 6.
8: Write to the SGACTLINE Register and SGMASK Register
9: VD/HD falling edge will update the serial writes from 8.
OPEN
STROBE output turns ON at the location specified in the
STROBON Registers (Addr x294 to Addr x299).
STROBEOFF Registers (Addr x29A to Addr x29F).
MSHUTOFF Registers (Addr x28D to Addr x292).
Addr x254) and SGMASK Register to configure the sensor
gates for EVEN field readout.
to reconfigure the sensor gates for Draft/Preview Mode output.
Write to the MSHUTON Register (Addr x287) to reopen
the mechanical shutter for Draft/Preview Mode.
SUBCK output resumes operation.
MSHUT output returns to the ON position (Active or
“Open”).
VSUB output returns to the OFF position (Inactive).
MODE 1
CLOSED
ODD
IMAGE READOUT
AD9891/AD9895
EVEN
OPEN