MAX9205EAI+ Maxim Integrated Products, MAX9205EAI+ Datasheet - Page 10

IC SERIALIZER LVDS 28-SSOP

MAX9205EAI+

Manufacturer Part Number
MAX9205EAI+
Description
IC SERIALIZER LVDS 28-SSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX9205EAI+

Function
Serializer
Data Rate
400Mbps
Input Type
LVTTL/LVCMOS
Output Type
LVDS
Number Of Inputs
10
Number Of Outputs
1
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Input Current
+/- 20 uA
Input Voltage Range (max)
3.6 V
Interface Type
Parallel LVCMOS/LVTTL
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Settling Time
500 ps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85��C
Digital Ic Case Style
SSOP
No. Of Pins
28
Filter Terminals
SMD
Control Interface
Serial
Supply Voltage Min
3V
Rohs Compliant
Yes
Data Rate Max
660Mbps
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10-Bit Bus LVDS Serializers
The serializers can operate in a variety of topologies.
Examples of double-terminated point-to-point, mul-
tidrop, point-to-point broadcast, and multipoint topolo-
gies are shown in Figures 11 through 14. Use 1%
surface-mount termination resistors.
A point-to-point connection terminated at each end in
the characteristic impedance of the cable or PCB
traces is shown in Figure 11. The total load seen by the
serializer is 50Ω. The double termination typically
Figure 11. Double-Terminated Point-to-Point
Figure 12. Multidrop
10
______________________________________________________________________________________
MAX9205
MAX9207
ASIC
PARALLEL
DATA IN
MAX9205
MAX9207
ASIC
MAX9206
MAX9208
Topologies
100Ω
SERIALIZED DATA
ASIC
MAX9206
MAX9208
reduces reflections compared to a single 100Ω termi-
nation. A single 100Ω termination at the deserializer
input is feasible and will make the differential signal
swing larger.
A serializer located at one end of a backplane bus dri-
ving multiple deserializers in a multidrop configuration
is shown in Figure 12. A 54Ω resistor at the far end ter-
minates the bus. This topology allows “broadcast” of
data with a minimum of interconnect.
100Ω
ASIC
MAX9206
MAX9208
MAX9206
MAX9208
PARALLEL
DATA OUT
ASIC
MAX9206
MAX9208
54Ω

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