PCA9541PW/03,118 NXP Semiconductors, PCA9541PW/03,118 Datasheet - Page 19

• Manufacturer Part Number: PCA9541PW/03,118
• Description: IC I2C 2:1 SELECTOR 16-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9541PW/03,118

• Package / Case: 16-TSSOP
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: PCA9541
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 7 V
• Logic Type: I2C Bus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Current: 25 mA
• Output Voltage: 2.3 V to 5.5 V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TSSOP
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1854-2; 935273316118; PCA9541PW/03-T

NXP Semiconductors
9. Characteristics of the I
PCA9541_7
Product data sheet
9.1 Bit transfer
9.2 START and STOP conditions
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see
Fig 9.
Fig 10. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
START condition
2
SDA
SCL
C-bus
S
Rev. 07 — 2 July 2009
Figure
2-to-1 I
10).
2
C-bus master selector with interrupt logic and reset
data valid
data line
stable;
Figure
allowed
change
of data
9).
STOP condition
mba607
PCA9541
P
© NXP B.V. 2009. All rights reserved.
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