PCA9541PW/03 NXP [NXP Semiconductors], PCA9541PW/03 Datasheet

PCA9541PW/03

Manufacturer Part Number

PCA9541PW/03

Description

2-to-1 I2C-bus master selector with interrupt logic and reset

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.PCA9541PW03.pdf (43 pages)

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1. General description

The PCA9541 is a 2-to-1 I

the controller card is removed for maintenance. The two masters (for example, primary

and back-up) are located on separate I

to select one master at a time. Either master at any time can gain control of the slave

devices if the other master is disabled or removed from the system. The failed master is

isolated from the system and will not affect communication between the on-line master

and the slave devices on the downstream I

Three versions are offered for different architectures. PCA9541/01 with channel 0

selected at start-up, PCA9541/02 with channel 0 selected after start-up and after STOP

condition is detected, and PCA9541/03 with no channel selected after start-up.

The interrupt outputs are used to provide an indication of which master has control of the

bus. One interrupt input (INT_IN) collects downstream information and propagates it to

the 2 upstream I

the previous bus master know that it is not in control of the bus anymore and to indicate

the completion of the bus recovery/initialization sequence. Those interrupts can be

disabled and will not generate an interrupt if the masking option is set.

A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a

STOP condition in order to set the downstream I

before actually switching the channel to the selected master.

An interrupt is sent to the upstream channel when the recovery/initialization procedure is

completed.

An internal bus sensor senses the downstream I

if a channel switch occurs during a non-idle bus condition. This function is enabled when

the PCA9541 recovery/initialization is not used. The interrupt signal informs the master

that an external I

and an interrupt will not be generated.

The pass gates of the switches are constructed such that the V

the maximum high voltage, which will be passed by the PCA9541. This allows the use of

different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate

with 5 V devices without any additional protection.

The PCA9541 does not isolate the capacitive loading on either side of the device, so the

designer must take into account all trace and device capacitances on both sides of the

device, and pull-up resistors must be used on all channels.

C-bus applications where system operation is required, even when one master fails or

C-bus slave devices. I

PCA9541

2-to-1 I

Rev. 05 — 1 October 2007

C-bus master selector with interrupt logic and reset

C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let

C-bus recovery/initialization needs to be performed. It can be disabled

C-bus commands are sent by either I

C-bus master selector designed for high reliability dual master

C-buses that connect to the same downstream

C-bus.

C-bus devices to an initialized state

C-bus trafﬁc and generates an interrupt

C-bus master and are used

pin can be used to limit

Product data sheet

Related parts for PCA9541PW/03

PCA9541PW/03 Summary of contents

Page 1

PCA9541 2-to-1 I Rev. 05 — 1 October 2007 1. General description The PCA9541 is a 2-to C-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. ...

Page 2

NXP Semiconductors External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant. An active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin LOW resets ...

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... Table 2. Type number PCA9541D/01 PCA9541PW/01 PCA9541BS/01 PCA9541D/02 PCA9541PW/02 PCA9541BS/02 PCA9541D/03 PCA9541PW/03 PCA9541BS/03 PCA9541_5 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thermal enhanced very thin quad ﬂ ...

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NXP Semiconductors 6. Block diagram PCA9541 SCL_MST0 SDA_MST0 RESET POWER-ON RESET V DD SCL_MST1 SDA_MST1 INT0 INT1 Fig 1. Block diagram of PCA9541 PCA9541_5 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic ...

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... SCL_MST1 PCA9541BS/ SDA_MST1 Transparent top view Rev. 05 — 1 October 2007 PCA9541 INT0 PCA9541PW/ PCA9541PW/ PCA9541PW/ INT1 002aab380 SDA_SLAVE SCL_SLAVE A3 A2 002aab381 © NXP B.V. 2007. All rights reserved INT_IN SDA_SLAVE SCL_SLAVE ...

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NXP Semiconductors 7.2 Pin description Table 3. Symbol INT0 SDA_MST0 SCL_MST0 RESET SCL_MST1 SDA_MST1 INT1 SCL_SLAVE SDA_SLAVE INT_IN V DD [1] HVQFN package die supply ground is connected to both the V pin must ...

Page 7

NXP Semiconductors 8. Functional description Refer to 8.1 Device address Following a START condition, the upstream master that wants to control the I make a status check must send the address of the slave it is accessing. The slave address ...

Page 8

NXP Semiconductors • During a write operation, the PCA9541 will acknowledge bytes sent to the IE and CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since read-only register. The 2 LSBs ...

Page 9

NXP Semiconductors • master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that longer connected ...

Page 10

NXP Semiconductors The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to be activated for a ‘functional interrupt test’. Remark: The regular way to proceed is that a master asks to take the control of ...

Page 11

NXP Semiconductors Table 6. Register 0 - Interrupt Enable (IE) register bit description Legend: * default value Bit Symbol Access Value 1 BUSINITMSK R/W 0 INTINMSK R/W [1] Default values are the same for PCA9541/01, PCA9541/02, PCA9541/03. 8.3.2 Register 1: ...

Page 12

NXP Semiconductors Table master reads its Control Register NMYBUS [1] MYBUS and NMYBUS is an exclusive-OR type function where: Equal values (‘00’ or ‘11’) means that the master reading its Control Register has ...

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NXP Semiconductors Table 11. Default Control Register values Type version Master Bit 7 NTESTON TESTON PCA9541/01 MST_0 0 MST_1 0 PCA9541/02 MST_0 0 at power-up MST_1 0 PCA9541/02 MST_0 0 after STOP MST_1 0 PCA9541/03 MST_0 0 MST_1 0 Table ...

Page 14

Table 12. Bus control sequence Read Control Register performed by the master Byte Status NBUSON BUSON NMYBUS MYBUS Byte [1] read Hex 0 bus off has control bus off no control bus off no ...

Page 15

NXP Semiconductors 8.4 Interrupt Status registers The PCA9541 provides 4 different types of interrupt: • To indicate to the former I • To indicate to the new I – The bus recovery/initialization has been performed and that the downstream channel ...

Page 16

NXP Semiconductors 8.4.3 Downstream interrupt An interrupt can also be generated by a downstream device by asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to ‘1’ by either master, INT0 ...

Page 17

NXP Semiconductors Table 14. Register 2 - Interrupt Status (ISTAT) register bit description Legend: * default value Bit Symbol Access Value [4] 2 BUSOK R only [4] 1 BUSINIT R only [2] 0 INTIN R only [1] Default values are ...

Page 18

NXP Semiconductors • PCA9541/03: default ‘no channel’ (no STOP detect) After power-up and/or insertion of the device in the main I connected to the downstream channel. The device is ready to receive a START condition and its address by a ...

Page 19

NXP Semiconductors 8.7 Voltage translation The pass gate transistors of the PCA9541 are constructed such that the V be used to limit the maximum voltage that will be passed from one I (1) maximum (2) typical (3) minimum Fig 8. ...

Page 20

NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be ...

Page 21

NXP Semiconductors 9.3 System conﬁguration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ ...

Page 22

NXP Semiconductors 9.5 Bus transactions slave address START condition R/W acknowledge from slave Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit Remark ...

Page 23

SDA_MST0 slave address command code register START condition R/W auto increment acknowledge from slave SCL_MST0 INT1 SCL_SLAVE SDA_SLAVE INT0 MASTER 1 ...

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NXP Semiconductors (1) SDA_MST0 slave address START condition R/W acknowledge from slave SCL_MST0 INT1 INT0 MASTER 1 has control of the bus ...

Page 25

NXP Semiconductors 10. Application design-in information 3.3 V 3.3 V Fig 17. Typical application 10.1 Speciﬁc applications The PCA9541 is a 2-to C-bus applications, where continuous maintenance and control monitoring is required even if one master fails ...

Page 26

NXP Semiconductors 10.2 High reliability systems In a typical multipoint application, shown in primary and back-up) are located on separate I downstream I or the PCA9541/02 for hot swap applications to provide high reliability of the I Fig 18. High ...

Page 27

NXP Semiconductors 10.3 Masters with shared resources Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541 can be used to separate the masters, as shown in ...

Page 28

NXP Semiconductors Fig 21. Gatekeeper multiplexer application 10.5 Bus initialization/recovery to initialize slaves without hardware reset 2 If the I C-bus is hung, I and Slave 2 in PCA9541/03 disconnects the bus when it is reset via the hardware reset ...

Page 29

NXP Semiconductors 11. Limiting values Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol tot T stg T ...

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NXP Semiconductors 12. Static characteristics Table 16. Static characteristics ( Symbol Parameter Supply V supply voltage DD I supply current DD I ...

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NXP Semiconductors Table 17. Static characteristics ( Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb ...

Page 32

NXP Semiconductors 13. Dynamic characteristics Table 18. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL f SCL clock frequency SCL(init/rec) (bus initialization/bus recovery) t bus free time between a STOP and BUF START condition t ...

Page 33

NXP Semiconductors [ total capacitance of one bus line in pF. b [5] Measurements taken with 1 k pull-up resistor and 50 pF load. [6] Resetting the device while actively communicating on the bus may cause glitches or ...

Page 34

NXP Semiconductors START SCL SDA RESET 50 % LEDx Fig 25. Deﬁnition of RESET timing 14. Test information Fig 26. Test circuitry for switching times PCA9541_5 Product data sheet 2 2-to-1 I C-bus master selector with interrupt logic and reset ...

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NXP Semiconductors 15. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

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NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm ...

Page 37

NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the ...

Page 38

NXP Semiconductors 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow soldering description” . 16.1 Introduction to soldering Soldering ...

Page 39

NXP Semiconductors 16.4 Reﬂow soldering Key characteristics in reﬂow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 40

NXP Semiconductors Fig 30. Temperature proﬁles for large and small components For further information on temperature proﬁles, refer to Application Note AN10365 “Surface mount reﬂow soldering description” . 17. Abbreviations Table 21. Acronym AI CDM DUT EEPROM ESD FRU HBM ...

Page 41

NXP Semiconductors 18. Revision history Table 22. Revision history Document ID Release date PCA9541_5 20071001 • Modiﬁcations: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have ...

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NXP Semiconductors 19. Legal information 19.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualiﬁcation Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 43

NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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