LM93CIMT/NOPB National Semiconductor, LM93CIMT/NOPB Datasheet - Page 41

• Manufacturer Part Number: LM93CIMT/NOPB
• Description: IC HARDWARE MONITOR 56-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM93CIMT/NOPB

• Applications: Monitors
• Interface: 2-Wire SMBus
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM93CIMT; *LM93CIMT/NOPB; LM93CIMT

Register
Address
Bit
7:6
16.0 Registers
16.4 BMC ERROR STATUS REGISTERS 40h–47h
The B_Error Status Registers contain several bits that each represent a particular error event that the LM93 can monitor. The
LM93 sets a given bit whenever the corresponding error event occurs. The BMC_ERR bit in the LM93 Status/Control register is
also set if any bit in the BMC Error Status registers is set. If enabled, ALERT is also asserted anytime BMC_ERR is set. The
exception to this is the fixed threshold error status bits in the PROCHOT Error Status registers. They have no influence on
BMC_ERR or ALERT.
Once a bit is set in the BMC Error Status registers, it is not automatically cleared by the LM93 if the error event goes away. Each
bit must be cleared by software. If software attempts to clear a bit while the error condition still exists, and the error is unmasked,
the bit does not clear. If the error is masked, the bit can be cleared even if the error condition still exists.
If the LM93 is in ASF mode, the BMC Error Status registers are both read-to-clear and write-one-to-clear. When not in ASF mode,
the registers are only write-one-to-clear.
Each register described in this section has a column labeled Sleep Masking. This column describes which error events are
masked in various sleep states. The sleep state of the system is communicated to the LM93 by writing to the Sleep State Control
register. If a sleep state in this column has a ‘*’ next to it, it denotes that the error event is optionally masked in that sleep mode,
depending on the Sleep State Mask registers.
16.4.1 Register 40h B_Error Status 1
0
1
2
3
4
5
40h
ZN1_ERR
ZN2_ERR
ZN3_ERR
ZN4_ERR
VRD1_ERR
VRD2_ERR
RES
Name
Read/
Write
RWC
Register
Status 1
B_Error
RWC This bit is set when the zone 1 temperature has fallen outside the zone 1
RWC This bit is set when the zone 2 temperature has fallen outside the zone 2
RWC This bit is set when the zone 3 temperature has fallen outside the zone 3
RWC This bit is set when the zone 4 temperature has fallen outside the zone 4
RWC This bit is set when the VRD1_HOT input has been asserted.
RWC This bit is set when the VRD2_HOT# input has been asserted.
Name
R/W
(Continued)
R
temperature limits.
temperature limits.
temperature limits.
temperature limits.
Reserved
Bit 7
RES
Bit 6
VRD2
_ERR
Bit 5
41
Description
VRD1
_ERR
Bit 4
ZN4_
Bit 3
ERR
ZN3_
Bit 2
ERR
ZN2_
Bit 1
ERR
ZN1_
Bit 0
ERR
S3*, S4/5*
S3*, S4/5*
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Masking
S3, S4/5
S3, S4/5
Sleep
none
none
N/A
Default
Value
00h