LM93CIMT/NOPB National Semiconductor, LM93CIMT/NOPB Datasheet - Page 51

• Manufacturer Part Number: LM93CIMT/NOPB
• Description: IC HARDWARE MONITOR 56-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM93CIMT/NOPB

• Applications: Monitors
• Interface: 2-Wire SMBus
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 56-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM93CIMT; *LM93CIMT/NOPB; LM93CIMT

Register
Address
Bit
16.0 Registers
16.5.7 Register 4Eh H_GPI Error Status
0
1
2
3
4
5
6
7
4Eh
GPI0_ERR
GPI1_ERR
GPI2_ERR
GPI3_ERR
GPI4_ERR
GPI5_ERR
GPI6_ERR
GPI7_ERR
Name
Read/
Write
RWC
Error Status
Register
RWC This bit is set whenever GPIO0 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO1 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO2 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO3 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO4 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO5 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO6 is driven low (unless masked via the GPI
RWC This bit is set whenever GPIO7 is driven low (unless masked via the GPI
H_GPI
Name
R/W
(Continued)
Error Mask register).
Error Mask register).
Error Mask register).
Error Mask register).
Error Mask register).
Error Mask register).
Error Mask register).
Error Mask register).
_ERR
Bit 7
GPI7
_ERR
GPI6
Bit 6
_ERR
Bit 5
GPI5
51
Description
_ERR
Bit 4
GPI4
_ERR
Bit 3
GPI3
_ERR
Bit 2
GPI2
_ERR
GPI1
Bit 1
_ERR
Bit 0
GPI0
S1*, S3*, S4/5*
S1*, S3*, S4/5*
S1*, S3*, S4/5*
S1*, S3*, S4/5*
S1*, S3*, S4/5*
S1*, S3*, S4/5*
S1*, S3*, S4/5*
S1*, S3*, S4/5*
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Masking
Sleep
Default
Value
00h