PDI1394P23BD-T ST-Ericsson Inc, PDI1394P23BD-T Datasheet - Page 32
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PDI1394P23BD-T
Manufacturer Part Number
PDI1394P23BD-T
Description
IC IEEE 1394 LINK CTRLR 64LQFP
Manufacturer
ST-Ericsson Inc
Datasheet
1.PDI1394P23BD-T.pdf
(42 pages)
Specifications of PDI1394P23BD-T
Applications
AV,TV, VTR
Interface
IEEE 1394
Voltage - Supply
3 V ~ 3.6 V
Package / Case
64-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PDI1394P23BD-T
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Philips Semiconductors
The sequence of events for a cancelled/null packet transmission is
as follows:
•
•
•
18.5 Interface reset and disable
The LLC controls the state of the PHY-LLC interface using the LPS
signal. The interface may be placed into a reset state, a disabled
state, or be made to initialize and then return to normal operation.
When the interface is not operational (whether reset, disabled, or in
the process of initialization) the PHY cancels any outstanding bus
request or register read request, and ignores any requests made via
the LREQ line. Additionally, any status information generated by the
PHY will not be queued and will not cause a status transfer upon
restoration of the interface to normal operation.
2001 Sep 06
Transmit operation initiated. PHY asserts grant on the CTL lines
followed by idle to hand over control of the interface to the link.
Optional Idle cycle. The link may assert at most one idle cycle
preceding assertion of hold. This idle cycle is optional; the link is
not required to assert idle preceding Hold.
Optional Hold cycles. The link may assert Hold for up to 47 cycles
preceding assertion of idle. These hold cycle(s) are optional; the
link is not required to assert hold preceding Idle.
CTL0, CTL1
2-port/1-port 400 Mbps physical layer interface
SYSCLK
D0–D7
00
00
(a)
11
00
Figure 19. Cancelled/Null Packet Transmission
(b)
00
(c)
32
•
•
The LPS signal may be either a level signal or a pulsed signal,
depending upon whether the PHY–LLC interface is a direct
connection or is made across an isolation barrier. When an isolation
barrier exists between the PHY and LLC (whether of the Philips
bus-holder type or Annex J type) the LPS signal must be pulsed. In
a direct connection, the LPS signal may be either a pulsed or a level
signal. Timing parameters for the LPS signal are given in Table 20.
PHY High-impedance Ctl and D Outputs
Null transmit termination. The null transmit operation is terminated
by the link asserting two cycles of idle on the CTL lines and then
releasing the interface and returning control to the PHY. Note that
the link may assert Idle for a total of 3 consecutive cycles if it
asserts the optional first idle cycle but does not assert hold. It is
recommended that the link assert 3 cycles of Idle to cancel a
packet transmission if no hold cycles are asserted. This ensures
that either the link or PHY controls the interface in all cycles.
After regaining control of the interface, the PHY shall assert at
least one cycle of Idle before any subsequent status transfer,
receive operation, or transmit operation.
Link Controls Ctl and D
01
00
(d)
00
PDI1394P23
Preliminary data
SV01763
(e)
00
00