TSI107D-100JE IDT, Integrated Device Technology Inc, TSI107D-100JE Datasheet
TSI107D-100JE
Specifications of TSI107D-100JE
Available stocks
Related parts for TSI107D-100JE
TSI107D-100JE Summary of contents
Page 1
Tsi107 Hardware Manual 80C2000_MA002_07 6024 Silver Creek Valley Road San Jose, California 95138 Telephone: (408) 284-8200 • FAX: (408) 284-3572 ©2009 Integrated Device Technology, Inc. ® November 3, 2009 Printed in U.S.A. ...
Page 2
Titlepage Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described ...
Page 3
... Tsi107 User Manual. Sections 1.1 to 1.7 of this document cover the following Tsi107 part numbers: Tsi107C-100JE, Tsi107C-100JETR, and Tsi107D-100JE. For changes to the electrical and physical characteristics for the 133 MHz Tsi107, part number Tsi107D-133LE, see Section 1.8, “133 MHz Tsi107 Hardware Specification Changes” ...
Page 4
Message Unit ( DMA Master Slave Five IRQs/ EPIC Interrupt 16 Serial Controller Interrupts Timers IEEE1149.1 JTAG Boundary Scan 80C2000_BK001_01 1.2 Features The Tsi107 provides an integrated high-bandwidth, high-performance interface for up to two ...
Page 5
Data-path buffering between memory interface and processor — Low-voltage TTL logic (LVTTL) interfaces — Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with programmable address strobe timing • 32-bit PCI interface operating up to ...
Page 6
Built-in PCI bus performance monitor facility • Debug features — Error injection/capture on data path — IEEE 1149.1 (JTAG)/test interface • Processor interface — Supports up to two PowerPC microprocessors with 60x bus interface — Supports various operating ...
Page 7
Absolute Maximum Ratings The tables in this section describe the Tsi107 DC electrical characteristics. Table 1 provides the absolute maximum ratings. 1 Characteristic Supply voltage—core Supply voltage—memory bus drivers Supply voltage—processor bus drivers Supply voltage—PCI and standard I/O buffers ...
Page 8
Recommended Operating Conditions Table 2 provides the recommended and tested operating conditions for the Tsi107. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Supply voltage Supply voltages for memory bus ...
Page 9
Figure 2 shows supply voltage sequencing and separation cautions 3 2 Voltage Regulator Delay Power Supply Ramp Up Reset Configuration Pins HRESET HRESET_CPU Notes: 1. Numbers associated with waveform separations correspond to caution ...
Page 10
Figure 3 shows the undershoot and overshoot voltage for the Tsi107 memory interface GND – 0 GND – 1.0 V Figure 4 and Figure 5 show the undershoot/overshoot voltage ...
Page 11
Over voltage Waveform Under voltage Waveform Figure 5. Maximum AC Waveforms for 5-V Signaling 1.4.1.3 DC Electrical Specifications Table 3 provides the DC electrical characteristics for the Tsi107. At recommended operating conditions (See Table 2) Characteristics Input high voltage PCI ...
Page 12
Table 3. DC Electrical Specifications (Continued) At recommended operating conditions (See Table 2) Characteristics Output high voltage I = driver dependent OH (BV DD All outputs except CPU_CLK[0: driver dependent OH (BV DD CPU_CLK[0:2] only Output low ...
Page 13
Output Driver Characteristics Table 4 provides information on the characteristics of the output drivers referenced in Table 17. The values are from the Tsi107 IBIS model and are not tested. Table 4. Drive Capability of Tsi107 Output Pins Programmable ...
Page 14
Power Characteristics Table 5 provides the preliminary power consumption estimates for the Tsi107. Power consumption on the PLL supply pin (AV ) and the DLL supply pin (LAV DD data. 25/50 Mode V I/O DD Power Power Typical ...
Page 15
Table 6. FC-PBGA Package Thermal Characteristics (Continued) Characteristic Junction-to-case Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board ...
Page 16
AC Electrical Characteristics This section provides the AC electrical characteristics for the Tsi107. After fabrication, functional parts are sorted by maximum core frequency as shown in Table 7 and Section 1.4.2.1, “Clock AC Specifications,” and tested for conformance ...
Page 17
Table 8. Clock AC Timing Specifications (Continued) At recommended operating conditions (See Table 2) with LV Num Characteristics and Conditions 9d SDRAM_CLK[0:3]/CPU_CLK[0:2] jitter 10 Internal PLL relock time 15 DLL lock range with DLL_STANDARD = 1 (default) 16 DLL lock ...
Page 18
Figure 6 shows PCI_SYNC_IN input clock timing. VM PCI_SYNC_IN Figure 6. PCI_SYNC_IN Input Clock Timing Diagram Figure 7 illustrates how the clock specifications in Table 8 relate to the Tsi107 clocking. Tsi107 Spec. 10 PLL OSC_IN Specs. 17–23 Note: ...
Page 19
Figure 8 and Figure 9 show the DLL locking range loop delay 1.8 27.9 ns clk loop Notes the period ...
Page 20
13.95 ns clk loop 0.55 clk 0 0 Notes the period of one SDRAM_SYNC_OUT clock cycle ...
Page 21
Input AC Timing Specifications Table 9 provides the input AC timing specifications. See Figure 10 and Figure 11. At recommended operating conditions (see Table 2) with LV Num 10a PCI input signals valid to PCI_SYNC_IN (input setup) 10b Memory ...
Page 22
Figure 10 shows input-output timing referenced to SDRAM_SYNC_IN and Figure 11 the input-output timing referenced to PCI_SYNC_IN . PCI_SYNC_IN PCI_SYNC_IN SDRAM_SYNC_IN SDRAM_SYNC_IN (Shown in 2:1 Mode) (Shown in 2:1 Mode) 10b,c,d Memory Memory Inputs/Outputs Inputs/Outputs Input Timing Input Timing ...
Page 23
Output AC Timing Specification Table 10 provides the processor bus AC timing specifications for the Tsi107. See Figure 10 and Figure 11. At recommended operating conditions (see Table 2) with LV Num Characteristic 12a PCI_SYNC_IN to output valid, 66 ...
Page 24
Figure 13 shows the AC test load for the Tsi107. Output Pin 1.4.2.4 PCI Signal Output Hold Timing In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 and 66 MHz PCI systems, the Tsi107 ...
Page 25
Figure 14 shows the PCI_HOLD_DEL effect on output valid and hold time. PCI_SYNC_IN 12a for 33 MHz PCI PCI_HOLD_DEL = 100 PCI Inputs/Outputs 33 MHz PCI 12a for 66 MHz PCI PCI_HOLD_DEL = 000 PCI Inputs/Outputs ...
Page 26
Timing Specifications 2 Table 12 provides the I C input AC timing specifications for the Tsi107. Table 12 recommended operating conditions (see Table 2) with LV Num Characteristic 1 Start condition hold ...
Page 27
Table 13 provides the I C frequency divider register (I2CFDR) information for the Tsi107. Table 13. Tsi107 Maximum FDR Hex Divider 20, 21 160, 192 22, 23, 24, 25 224, 256, 320, 384 0, 1 288, ...
Page 28
Table 14 provides the I C output AC timing specifications for the Tsi107. Table 14 recommended operating conditions (see Table 2) with LV Num Characteristic 1 Start condition hold time 2 Clock low period 3 SCL/SDA ...
Page 29
Figure 15 through Figure 18 show I VM SCL 1 SDA 5 VM SCL 8 SDA DFFSR Filter Clock SDA Note: DFFSR filter clock is the SDRAM_CLK/CPU_CLK clock times DFFSR value. VM SCL/SDA realtime Delay VM SCL/SDA qualified Note: The ...
Page 30
PIC Serial Interrupt Mode AC Timing Specifications Table 15 provides the PIC serial interrupt mode AC timing specifications for the Tsi107. Table 15. PIC Serial Interrupt Mode AC Timing Specifications At recommended operating conditions (see Table 2) with ...
Page 31
S_CLK S_INT Figure 20. PIC Serial Interrupt Mode Input Timing Diagram 1.4.2.7 IEEE 1149.1 (JTAG) AC Timing Specifications Table 16 provides the JTAG AC timing specifications for the Tsi107 while in the JTAG operating mode. Table 16. JTAG AC Timing ...
Page 32
Figure 21 shows the JTAG clock input timing diagram. TCK 3 Figure 21. JTAG Clock Input Timing Diagram Figure 22 shows the JTAG TRST timing diagram. TCK TRST Figure 23 shows the JTAG boundary scan timing diagram. TCK Data ...
Page 33
Figure 24 shows the test access port timing diagram. TCK TDI, TMS TDO TDO 1.5 Package Description This section details the Tsi107 package parameters, pin assignments, and dimensions. 1.5.1 Package Parameters The package parameters for the Tsi107 include the following: ...
Page 34
Pin Assignments and Package Dimensions Figure 25 shows the top surface, side profile, and pinout for the Tsi107, 503 FC-PBGA package. NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M-1994. 2. DIMENSIONS IN MILLIMETERS. 3. MAXIMUM SOLDER BALL DIAMETER ...
Page 35
Pinout Listings Table 17 provides the pinout listing for the Tsi107, 503 FC-PBGA package. Name A[0:31] AE22, AE16, AA14, AE17, AD21, AD14, AD20, AB16, AB20, AB15, AA20, AD13, Y15, AE12, AD15, AB9, AB14, AA8, AC13, Y12, Y11, AE15, AE13, ...
Page 36
Name TEA AB11 TS AA10 TSIZ[0:2] AE19,AD18,AB18 TT[0:4] AD19,AC19,AB19,AA19,AA18 WT AC16 AD[31:0] N23, N21, M20, M21, M22, M24, M25, L20, L22, K25, K24, K23, K21, J20, J24, J25, H20, F24, E25, F21, E24, E22, D25, A25, B25, A23, B23, ...
Page 37
Name MDH[0:31] M6, L4, L6, K2, K4, K5, J4, J6, H4, H5, G3, G5, G6, F5, F1, E1, B14, D15, B15, E16, D16, C16, D18, D17, B17, F18, E19, E20, B19, B20, B21, A22 MDL[0:31] M5, L1, L2, K1, K3, ...
Page 38
Name SCL AB25 SDA AB24 CKO V20 CPU_CLK[0:2] AA12, AA13, AB12 OSC_IN U22 PCI_CLK [0:4] R25, P24, R24, N24, N25 PCI_SYNC_IN P20 PCI_SYNC_OUT P25 SDRAM_CLK [0:3] D14, D13, E12, E14 SDRAM_SYNC_IN E13 SDRAM_SYNC_OUT D12 HRESET AA23 HRESET_CPU AB21 MCP ...
Page 39
Name TRIG_IN W22 TRIG_OUT W21 TRST AA24 AV AE24 DD GND AA21, AB22, AC11, AC14, AC17, AC20, AC23, AC3, AC5, AC8, AD24, AE25, C12, C15, C18, C21, C23, C3, C6, C9, E3, F10, F16, F20, F23, F6, G11, G13, G15, ...
Page 40
Name FTP[2:3] R20, D24 MTP[1:2] B12, B13 Notes: 1. This pin has an internal pull-up resistor which is enabled only when the Tsi107 is in reset state. The value of the internal pull-up resistor is not guaranteed, but is ...
Page 41
PLL Configuration The Tsi107 internal PLL is configured by the PLL_CFG[0:3] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set the core/memory/processor PLL (VCO) frequency of operation for the PCI-to-core/memory/processor frequency multiplying, if any. All ...
Page 42
AV the 500-kHz to 10-MHz resonant frequency range of the PLLs. A separate circuit similar to the one shown in Figure 26 using surface mount capacitors with minimum effective series inductance ...
Page 43
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices and then returned to the SDRAM_SYNC_IN input of the Tsi107. The trace length may be used to skew or adjust the timing window as needed. The ...
Page 44
T = ambient temperature for the package ( junction-to-ambient thermal resistance (C/W) power dissipation in the package (W) D The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy ...
Page 45
The board designer can choose between several types of heat sinks to place on the Tsi107. Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, ...
Page 46
Figure 29. Thermal Performance of Select Thermal Interface Material Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 28). ...
Page 47
Thermal Interface Materials For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: + ( where die-junction temperature inlet cabinet ...
Page 48
... MHz Tsi107 Hardware Specification Changes This section shows changes applicable to the 133 MHz Tsi107, part numbers Tsi107D-133LE and Tsi107D-133LEY. These changes are revisions to the recommended operating conditions and electrical specifications from those described in the previous sections of this document. Table 19. Part Numbers addressed by this section ...
Page 49
Table 21. Power Consumption for the 133 MHz Tsi107 (Continued) CI_SYNC_IN/Core Frequency (MHz) 66/133 Mode Sleep Notes: 1. Power is extrapolated 2 All clock drivers enabled. 1.8.2 AC Electrical Characteristic Changes The following ...
Page 50
Table 23. Maximum I FDR 2 Hex 2E, 2F, 30 32, 33, 34, 35 10, 11 12, 13, 36, 37, 38, 39 14, 15 16, 17, 3A, 3B, 3C, 3D ...
Page 51
... Clock Off Not Usable Table 25. IDT Part Numbers Current IDT Part Number Tsi107D-66JE Tsi107D-66JEY Tsi107C-100JE Tsi107D-100JEY Tsi107D-100JE Tsi107D-133LE Tsi107D-133LEY PCI:Core VCO Ratio Multiplier Off Off Obsolete Motorola Part Number XPC107APX66LD N/A XPC107APX100LC N/A XPC107APX100LD XPC107APX133WD N/A ...
Page 52
Part Number Information The IDT “Tsi” part numbering system is explained as follows. Tsi NNN(N) - SS( (Z#) • – Indicates optional characters. • Tsi – IDT product identifier. • NNNN – Product ...
Page 53
Y - RoHS Compliant (Flip Chip) – These products contain only one of the six restricted substances: Lead (Pb). These flip-chip products are RoHS compliant through the Lead exemption for Flip Chip technology, Commission Decision 2005/747/EC, which allows Lead ...